Visible to Intel only — GUID: sam1412835926615
Ixiasoft
Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
Intel® Arria® 10 and Intel® Cyclone® 10 GX GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412835926615
Ixiasoft
GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example
The synthesizable design example is a compilation-ready Platform Designer system that you can include in an Intel® Quartus® Prime project.
Generating and Using the Design Example
To generate the synthesizable Intel® Quartus® Prime design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following command:
quartus_sh -t make_qii_design.tcl [device_name]
The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.