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Release Information for GPIO Intel® FPGA IP
GPIO Intel® FPGA IP Features
GPIO Intel® FPGA IP Data Paths
GPIO Intel® FPGA IP Interface Signals
Verifying Resource Utilization and Design Performance
GPIO Intel® FPGA IP Parameter Settings
Register Packing
GPIO Intel® FPGA IP Timing
GPIO Intel® FPGA IP Design Examples
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
Intel® Arria® 10 and Intel® Cyclone® 10 GX GPIO Intel® FPGA IP User Guide Archives
Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
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Delay Elements
The Intel® Quartus® Prime software does not automatically set delay elements to maximize slack in the I/O timing analysis. To close the timing or maximize slack, set the delay elements manually in the Intel® Quartus® Prime settings file (.qsf).
Delay Element | .qsf Assignment |
---|---|
Input Delay Element | set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63> |
Output Delay Element | set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15> |
Output Enable Delay Element | set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15> |