Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Public
Document Table of Contents

1.1. Intended Audience

The intended audience consists of FPGA RTL designers developing AFUs for the Acceleration Stack on the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) and the hardware platforms (referred to as Intel® FPGA PAC throughout this document).