JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683113
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.10.3.1. Functions in main.c Source File

The function prototypes of the functions listed in the table below can be found in the functions.h header file located in the software folder.

Table 22.  Functions in main.c
Function Prototype Description

int StringIsNumeric (

char *string)

 Tests whether the string is numeric. Returns 1 if true, 0 if false.

void DelayCounter(

alt_u32 count)

 Delay counter. Counts up to count ticks, each tick is roughly 1 second.

int Status (

char *options[][])

 Executes report link status command according to the options. Returns 0 if success, 1 if fail, 2 if sync errors found, 4 if pattern checker errors found, 6 if both sync errors and pattern checker errors found

int Loopback (

char *options[][],

int *held_resets,

int dnr)

 Executes loopback command according to the options. Returns 0 if success, 1 if fail

int SourceDest (

char *options[][],

int *held_resets,

int dnr)

 Executes source or destination datapath selection command according to the options. Returns 0 if success, 1 if fail

int Test (

char *options[][],

int *held_resets)

 Executes test mode command according to the options. Test mode:
  • Set source/destination datapath selection to PRBS test pattern generator or checker.
  • Set transceiver to serial loopback mode.

Returns 0 if success, 1 if fail.
void Sysref (void) Pulse SYSREF signal one time (one-shot)
void ResetHard (void) Triggers full hardware reset sequence through the PIO control registers.

int ResetSeq (

int link,

int *held)

 Performs full hardware reset sequence through the software interface on the indicated link. Returns 0 if success, 1 if fail.

int ResetForce (

int link,

int reset_val,

int hold_release,

int *held_resets)

 Forces reset assertion or deassertion on submodule resets indicated by reset_val for the indicated link. The function also decides whether to assert and hold (hold_release=2), deassert (hold_release=1), or pulse (hold_release=0) the indicated resets. The function has mechanisms using the global held_resets flag to ensure that held resets that are not the target of the reset force function are not affected by it. Returns 0 if success, 1 if fail.

int Reset_X_L_F_Release (

int link,

int *held_resets)

 Deassert the transceiver, link, and frame resets. The function deasserts the TX transceiver reset first, waits until the TX transceiver ready signal asserts, then deasserts the TX link and TX frame resets. The function then repeats the above actions for the RX side. Returns 0 if success, 1 if fail.
void InitISR (void) Initializes the interrupt controllers for the following peripherals:
  • JESD204B IP core TX CSR
  • JESD204B IP core RX CSR
  • SPI Master

The timer and JTAG UART interrupt controllers are disabled. Modify the function to enable it. Refer to the Nios II Software Developer’s Handbook for more details on writing ISRs.

static void ISR_JESD_RX (

void * context)

 JESD204B IP core RX ISR. Upon an interrupt event (IRQ asserted), the function reads the RX JESD204B CSR rx_err0 and rx_err1 registers and reports the error code. After that, the ISR clears all valid and active status registers in the rx_err0 and rx_err1 registers. Refer to the Nios II Software Developer’s Handbook for more details on writing ISRs.

static void ISR_JESD_TX (

void * context)

 JESD204B IP core TX ISR. Upon an interrupt event (IRQ asserted), the function reads the TX JESD204B CSR tx_err registers and reports the error code. After that, the ISR clears all the valid and active status registers in the tx_err registers. Refer to the Nios II Software Developer’s Handbook for more details on writing ISRs.

static void ISR_SPI (

void * context)

 SPI Master interrupt service routine (ISR). Upon interrupt event (IRQ assert), clears IRQ flag and return. Refer to the Nios II Software Developer’s Handbook for more details on writing ISRs.
Level Two Title