JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.4. Presets

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. Select the presets at the lower right window in the parameter editor.

The presets are applicable for JESD204B IP configurations that generate design examples. You can select one of the presets available for your target device to quickly generate a design example without having to set each parameter in the IP tab and verify that the specified parameters match the supported configurations. You can manually change any of the IP and example design parameters in the Platform Designer user interface after selecting a preset. However, you must ensure that your parameter selection falls within the supported configuration ranges detailed in Supported Configurations for design example to generate successfully.

Note: Selecting a preset overwrites any pre-existing parameter selections for the IP core under the IP tab.
Table 9.  Preset Settings
JESD204B IP Parameters Preset 1

JESD204B Example Design

(LMF = 222, 6.144 Gbps)

 Preset 2

JESD204B Example Design

(LMF = 888, 6.144 Gbps)
Wrapper Options Both Base and PHY Both Base and PHY
Data Path Duplex Duplex
JESD204B Subclass 1 1
Data Rate 6144 Mbps 6144 Mbps
PCS Option Enabled Hard PCS Enabled Hard PCS
Bonding Mode Non-bonded Non-bonded
PLL/CDR Reference Clock Frequency 153.6 MHz 153.6 MHz
Enable Bit Reversal and Byte Reversal No No
Enable Transceiver Dynamic Reconfiguration No No
L 2 8
M 2 8
Enable manual F configuration No Yes
F 2 8
N 16 12
N’ 16 12
S 1 5
K 16 32
Enable Scramble (SCR) No No
CS 0 0
CF 0 0
High Density User Data Format (HD) 0 0
Enable Error Code Correction (ECC_EN) No No
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