JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.2.3. Supported Configurations

The design examples only support a limited set of JESD204B IP parameter configurations. The IP parameter editor allows you to generate a design example only if the parameter configurations matches the following table.
Note: If you are not able to generate a design example that fully matches your desired parameter settings, choose the closest allowable parameter values for generation. Modify the post-generated design parameters manually in the Intel® Quartus® Prime software to match your desire parameter settings. Refer to the JESD204B Intel® FPGA IP User Guide for more details on the rules and ranges that govern each IP and transport layer parameter. Refer to Customizing the Design Example for more information about customizing the design example.
Table 7.  Supported JESD204B IP Parameter Configurations (L, M, F Values)
L M F
1 1 2
1 1 3
1 1 4
1 1 8
1 2 3
1 2 4
1 2 8
1 4 8
2 1 1
2 1 2
2 1 3
2 1 4
2 1 8
2 2 2
2 2 3
2 2 4
2 2 8
2 4 3
2 4 4
2 4 8
2 8 8
4 1 1
4 1 2
4 1 3
4 1 4
4 2 1
4 2 2
4 2 3
4 2 4
4 2 8
4 4 2
4 4 3
4 4 4
4 4 8
4 8 3
4 8 4
4 8 8
4 16 8
6 1 1
6 3 1
8 1 1
8 1 2
8 2 1
8 2 2
8 2 3
8 2 4
8 2 8
8 4 1
8 4 2
8 4 3
8 4 4
8 4 8
8 8 2
8 8 3
8 8 4
8 8 8
8 16 3
8 16 4
8 16 8
8 32 8
Table 8.  Supported JESD204B IP Core Parameter ConfigurationsTable lists the parameters for the JESD204B IP. The JESD204B IP parameters are governed by various rules and ranges that are described in the JESD204B Intel® FPGA IP User Guide. Please refer to the JESD204B Intel® FPGA IP User Guide for more details on the legal parameter values. The value ranges given below should be considered as a subset of the allowable values described in the JESD204B Intel® FPGA IP User Guide.
JESD204B IP Parameters Values
Wrapper Options Both Base and PHY
Data Path
  • Receiver
  • Transmitter
  • Duplex
JESD204B Subclass 1
Data Rate

Any valid value4

PCS Option
  • Enabled Hard PCS
  • Enabled Soft PCS
Bonding Mode
  • Bonded
  • Non-bonded
PLL/CDR Reference Clock Frequency Any valid value
Enable Bit Reversal and Byte Reversal Any valid value
Enable Transceiver Dynamic Reconfiguration

Any valid value
L
  • 1
  • 2
  • 4
  • 65
  • 8
M
  • 1
  • 2
  • 36
  • 4
  • 8
  • 16
  • 32
Enable manual F configuration
  • No
  • Yes only for the following configuration:

    L=8, M=8, F=8, S=5, N’=12, N=12
F
  • Auto calculated
  • Manual F configuration only allowed for the following configuration:

    L=8, M=8, F=8, S=5, N’=12, N=12
N Integer, range 12 – 16
N’
  • 16
  • 12 only for the following configuration:

    L=8, M=8, F=8, S=5, N=12
S Any valid value
K Any valid value
Enable Scramble (SCR) Any valid value
CS Integer, range 0 – 3
CF 0
High Density User Data Format (HD)
  • 0
  • 1 only for F=1
Enable Error Code Correction (ECC_EN) Any valid value
Related Information
4 Refer to JESD204B Intel® FPGA IP User Guide for more details on maximum and minimum data rates for your target device.
5 L=6 is only allowed when F=1
6 M=3 is only allowed for L=6
Level Two Title