AN 775: Generating Initial I/O Timing Data: for Intel FPGAs

Download PDF
ID 683103
Date 12/08/2019
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation 1.6. AN 775: Generating Initial I/O Timing Data Document Revision History
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs

1.3. Step 3: Specify Device Operating Conditions

Follow these steps to update the timing netlist and set operating conditions for timing analysis following full compilation:
  1. Click Tools > Timing Analyzer.
  2. In the Task pane, double-click Update Timing Netlist. The timing netlist updates with full compilation timing information that accounts for the pin constraints you make.
    Figure 5. Task Pane in the Timing Analyzer
  3. Under Set Operating Conditions, select one of the available timing models, such as Slow vid3 100C Model or Fast vid3 100C Model.
    Figure 6. Set Operating Conditions in the Timing Analyzer
Level Two Title