AN 775: Generating Initial I/O Timing Data: for Intel FPGAs

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ID 683103
Date 12/08/2019
Public

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Document Table of Contents
Document Table of Contents x
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs x
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device 1.2. Step 2: Define I/O Standard and Pin Locations 1.3. Step 3: Specify Device Operating Conditions 1.4. Step 4: View I/O Timing in Datasheet Report 1.5. Scripted I/O Timing Data Generation 1.6. AN 775: Generating Initial I/O Timing Data Document Revision History
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs

1.6. AN 775: Generating Initial I/O Timing Data Document Revision History

Document Version Intel® Quartus® Prime Version Changes
2019.12.08 19.3
  • Revised title to reflect content.
  • Added support for Intel® Stratix® 10 and Intel® Agilex™ FPGAs.
  • Added step numbers to flow.
  • Added timing parameter diagrams.
  • Updated screenshots to reflect latest version.
  • Updated links to related documents.
  • Applied latest product naming and style conventions.
2016.10.31 16.1
  • First public release.
Level Two Title