Introduction to Intel® FPGA IP Cores

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ID 683102
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA IP Cores
1. Introduction to Intel® FPGA IP Cores x
1.1. IP Catalog and Parameter Editor 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Best Practices for Intel® FPGA IP 1.4. IP General Settings 1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 1.7. Modifying an IP Variation 1.8. Upgrading IP Cores 1.9. Simulating Intel® FPGA IP Cores 1.10. Synthesizing IP Cores in Other EDA Tools 1.11. Support for the IEEE 1735 Encryption Standard 1.12. Introduction to Intel® FPGA IP Cores Archives 1.13. Introduction to Intel® FPGA IP Cores Revision History
1.1. IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores x
1.2.1. Intel® FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. Intel FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1.8. Upgrading IP Cores x
1.8.1. Upgrading IP Cores at Command-Line 1.8.2. Migrating IP Cores to a Different Device 1.8.3. Troubleshooting IP or Platform Designer System Upgrade
1.9. Simulating Intel® FPGA IP Cores x
1.9.1. Supported Simulators 1.9.2. Supported Simulation Flows 1.9.3. Generating IP Simulation Files 1.9.4. Scripting IP Simulation 1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.9.4. Scripting IP Simulation x
1.9.4.1. Generating a Combined Simulator Setup Script
1.9.4.1. Generating a Combined Simulator Setup Script x
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts 1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.9.5.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.9.5.2. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
1.10. Synthesizing IP Cores in Other EDA Tools x
1.10.1. Instantiating IP Cores in HDL
1.10.1. Instantiating IP Cores in HDL x
1.10.1.1. Accessing HDL Code Templates
1.10.1.1. Accessing HDL Code Templates x
1.10.1.1.1. Example Top-Level Verilog HDL Module 1.10.1.1.2. Example Top-Level VHDL Module
1. Introduction to Intel® FPGA IP Cores

1.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)

The Intel® Quartus® Prime Standard Edition legacy parameter editors generate one of the following output file structures for individual IP cores:
Figure 10. IP Core Generated Files (Legacy Parameter Editors)


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