4.2. Erasure Decoder IP Core Signals
| Name | Avalon-ST Type | Direction | Description |
|---|---|---|---|
| clk_clk | clk | Input | The main system clock. The whole IP core operates on the rising edge of clk_clk . |
| reset_reset_n | reset_n | Input | An active low signal that resets the entire system when asserted. You can assert this signal asynchronously. However, you must deassert it synchronous to the clk_clk signal. When the IP core recovers from reset, ensure that the data it receives is a complete packet. |
| Name | Avalon-ST Type | Direction | Description |
|---|---|---|---|
| in_ready | ready | Output | Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the in_ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge. |
| in_valid | valid | Input | Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal. |
| in_data[] | data | Input | Data input containing the codeword symbols. Valid only when in_valid is asserted. The in_data signal is a vector containing C x PAR symbols. If PAR < N, the codeword of each channel arrives over several cycles. |
| in_era | data | Input | Data input that indicates which symbols are erasures. Valid only when in_valid is asserted. It is a vector containing C x PAR bits. |
| out_ready | ready | Input | Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal. |
| out_valid | valid | Output | Data valid signal. The IP core asserts the out_valid signal high, whenever a valid output is on out_data. |
| out_data | data | Output | Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered. It is a vector containing C x N symbols. |
| out_error | error | Output | Indicates non-correctable codeword. |
An asserted in_valid signal indicates valid data.
Each codeword can arrive over several cycles, depending on the parallelism parameter. The design tracks the structure of the input, so it requires no packet boundaries on the interface. The design's Number of channels in parallel increases throughput by replicating the functional units for all the concurrent channels. This design does not use Avalon-ST interface multiple channel support.
When the decoder asserts the out_valid signal, it provides valid data on out_data. It outputs C codewords per cycle, where C is the number of channels in parallel. The IP core asserts out_error signal when it receives a non-correctable codeword, i.e.: when the IP core exceeds erasure correction capability.