Erasure Decoder Reference Design

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ID 683099
Date 5/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Erasure Decoder Reference Design 2. Erasure Decoder Functional Description 3. Erasure Decoder IP Core Parameters 4. Erasure Decoder Interfaces and Signals
4. Erasure Decoder Interfaces and Signals x
4.1. Avalon-ST Interfaces in DSP IP Cores 4.2. Erasure Decoder IP Core Signals
1. About the Erasure Decoder Reference Design
2. Erasure Decoder Functional Description
3. Erasure Decoder IP Core Parameters
4. Erasure Decoder Interfaces and Signals

1. About the Erasure Decoder Reference Design

Updated for:
Intel® Quartus® Prime Design Suite 17.0
The Erasure Decoder is a particular type of Reed-Solomon decoder that uses a non-binary, cyclic, linear block error correction code.

In a Reed-Solomon decoder with erasure decoding capability, the number of errors (E) and erasures (E’) that you can correct is:

n – k = 2E + E’

Where n is the block length and k is the message length (n-k equals the number of parity symbols).

The Erasure Decoder only considers erasures, so the correction capability can reach the maximum given by n-k. The decoder receives as input the erasure locations, typically provided by the demodulator within the coding system, which can indicate certain received code symbols as unreliable. The design should not not exceed the erasure correction capability. The design treats symbols that it indicates as erasure as zero value.

Features

  • Targets Stratix® 10 devices
  • Corrects erasures
  • Parallel operation
  • Flow control
Level Two Title