Nios® V Processor Intel® FPGA IP Release Notes

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ID 683098
Date 6/21/2022
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Document Table of Contents x
1. Nios® V Processor Intel® FPGA IP Release Notes 2. Nios® V Embedded Processor Design Handbook Archives
1. Nios® V Processor Intel® FPGA IP Release Notes x
1.1. Nios® V/m Processor Intel® FPGA IP v21.3.0 1.2. Nios® V/m Processor Intel® FPGA IP v21.2.0 1.3. Nios® V/m Processor Intel® FPGA IP v21.1.1 1.4. Nios® V/m Processor Intel® FPGA IP v21.1.0
1. Nios® V Processor Intel® FPGA IP Release Notes
2. Nios® V Embedded Processor Design Handbook Archives

1.2. Nios® V/m Processor Intel® FPGA IP v21.2.0

Table 2.  v21.2.0 2022.04.04
Intel® Quartus® Prime Version Description Impact
22.1
  • Added new design examples in the Nios® V/m Processor Intel FPGA IP core parameter editor:
    • uC/TCP-IP IPerf Example Design
    • uC/TCP-IP Simple Socket Server Example Design
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  • Bug Fix:
    • Addressed issues causing unreliable accesses to the MARCHID, MIMPID, and MVENDORID CSRs.
    • Enabled reset capability from the debug module to allow the core to be reset through a debugger.
    • Enabled support for trigger. The Nios® V processor core supports 1 trigger.
    • Addressed reported synthesis warnings and lint issues.
    • Addressed an issue from the debug ROM that caused a corruption in the return vector.
    • Fixed an issue which prevented access to GPR 31 from the debug module.
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