Nios® V Processor Intel® FPGA IP Release Notes

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ID 683098
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Intel® FPGA IP Release Notes 2. Nios® V Embedded Processor Design Handbook Archives
1. Nios® V Processor Intel® FPGA IP Release Notes x
1.1. Nios® V/m Processor Intel® FPGA IP v21.3.0 1.2. Nios® V/m Processor Intel® FPGA IP v21.2.0 1.3. Nios® V/m Processor Intel® FPGA IP v21.1.1 1.4. Nios® V/m Processor Intel® FPGA IP v21.1.0
1. Nios® V Processor Intel® FPGA IP Release Notes
2. Nios® V Embedded Processor Design Handbook Archives

1.3. Nios® V/m Processor Intel® FPGA IP v21.1.1

Table 3.  v21.1.1 2021.12.13
Intel® Quartus® Prime Version Description Impact
21.4
  • Bug Fix:
    • Trigger registers accessible but triggers were not supported issue fixed.
Illegal instruction exception prompted when accessing trigger registers.
  • Added new Design Example in the Nios® V/m Processor Intel FPGA IP core parameter editor.
    • GSFI Bootloader Example Design
    • SDM Bootloader Example Design
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