MAX® 10 External Memory Interface User Guide

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ID 683087
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 External Memory Interface Overview 2. MAX® 10 External Memory Interface Architecture and Features 3. MAX® 10 External Memory Interface Design Considerations 4. MAX® 10 External Memory Interface Implementation Guides 5. UniPHY IP References for MAX® 10 Devices 6. MAX® 10 External Memory Interface User Guide Archives 7. Document Revision History for the MAX® 10 External Memory Interface User Guide
1. MAX® 10 External Memory Interface Overview x
1.1. MAX® 10 External Memory Interface Support and Performance
2. MAX® 10 External Memory Interface Architecture and Features x
2.1. MAX® 10 I/O Banks for External Memory Interface 2.2. MAX® 10 DQ/DQS Groups 2.3. MAX® 10 External Memory Interfaces Maximum Width 2.4. MAX® 10 Memory Controller 2.5. MAX® 10 External Memory Read Datapath 2.6. MAX® 10 External Memory Write Datapath 2.7. MAX® 10 Address/Command Path 2.8. MAX® 10 PHY Clock (PHYCLK) Network 2.9. Phase Detector for VT Tracking 2.10. On-Chip Termination 2.11. Phase-Locked Loop 2.12. MAX® 10 Low Power Feature
2.5. MAX® 10 External Memory Read Datapath x
2.5.1. DDR Input Registers
2.6. MAX® 10 External Memory Write Datapath x
2.6.1. DDR Output Registers
3. MAX® 10 External Memory Interface Design Considerations x
3.1. MAX® 10 DDR2 and DDR3 Design Considerations 3.2. LPDDR2 Design Considerations 3.3. Guidelines: DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation 3.4. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 3.5. Guidelines: Reading the MAX® 10 Pin-Out Files
3.1. MAX® 10 DDR2 and DDR3 Design Considerations x
3.1.1. DDR2/DDR3 External Memory Interface Pins 3.1.2. DDR2/DDR3 Recommended Termination Schemes for MAX® 10 Devices
3.1.1. DDR2/DDR3 External Memory Interface Pins x
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.1.1.2. Data Mask Pins 3.1.1.3. DDR2/DDR3 Error Correction Coding Pins 3.1.1.4. DDR2/DDR3 Address and Control/Command Pins 3.1.1.5. Memory Clock Pins
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.1.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
3.2. LPDDR2 Design Considerations x
3.2.1. LPDDR2 External Memory Interface Pins 3.2.2. LPPDDR2 Power Supply Variation Constraint 3.2.3. LPDDR2 Recommended Termination Schemes for MAX® 10 Devices
3.2.1. LPDDR2 External Memory Interface Pins x
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.2.1.2. Data Mask Pins 3.2.1.3. LPDDR2 Address and Control/Command Pins 3.2.1.4. Memory Clock Pins
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.2.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for LPDDR2
4. MAX® 10 External Memory Interface Implementation Guides x
4.1. UniPHY IP Core 4.2. LPDDR2 External Memory Interface Implementation 4.3. DDR2 and DDR3 External Memory Interface Implementation
4.2. LPDDR2 External Memory Interface Implementation x
4.2.1. Supported LPDDR2 Topology
4.3. DDR2 and DDR3 External Memory Interface Implementation x
4.3.1. MAX® 10 Supported DDR2 or DDR3 Topology
5. UniPHY IP References for MAX® 10 Devices x
5.1. UniPHY Parameter Settings for MAX® 10
5.1. UniPHY Parameter Settings for MAX® 10 x
5.1.1. UniPHY Parameters—PHY Settings 5.1.2. UniPHY Parameters—Memory Parameters 5.1.3. UniPHY Parameters—Memory Timing 5.1.4. UniPHY Parameters—Board Settings 5.1.5. UniPHY Parameters—Controller Settings 5.1.6. UniPHY Parameters—Diagnostics
1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide

3.1.2. DDR2/DDR3 Recommended Termination Schemes for MAX® 10 Devices

If you are creating interfaces with multiple DDR2 or DDR3 components where the address, command, and memory clock pins are connected to more than one load, follow these steps:

  1. Simulate the system to get the new slew rate for the DQ/DQS, DM, address and command, and clock signals.
  2. Use the derated tIS and tIH specifications from the DDR2 or DDR3 datasheet based on the simulation results.
  3. If timing deration causes your interface to fail timing requirements, consider duplication of these signals to lower their loading, and hence improve timing.
Note: Class I and Class II termination schemes in the following tables refer to drive strength and not physical termination.
Table 5.  Termination Recommendations for MAX® 10 DDR2 Component
Signal Type SSTL 18 I/O Standard FPGA–End Discrete Termination Memory–End Termination 1 Memory I/O Standard
DQ/DQS Class I Rs = 50 Ω 50 Ω parallel to VTT discrete ODT75 4 HALF 5
DM Class I Rs = 50 Ω — ODT754 HALF5
Address and command Class I with maximum drive strength — 56 Ω parallel to VTT discrete —
Clock Differential Class I Rs = 50 Ω —
  • x1 = 100 Ω differential6
  • x2 = 200 Ω differential7
—
Table 6.  On Board Termination Recommendation for MAX® 10 DDR3 ComponentFor MAX® 10 devices, on board termination is required for DDR3 component.
I/O Standard RS OCT On Board Termination
FPGA–End Memory-End
SSTL 15 Class 1 50 Ω without calibration 80 Ω resistor 40 Ω resistor
Table 7.  Supported External Memory Interface Termination Scheme for DDR3 and DDR2
Memory Interface Standard I/O Standard RS OCT RUP, RDN (Ω)
DDR3 SSTL-15 25 25
34 34
40 40
50 50
DDR3L SSTL-135 34 34
40 40
DDR2 SSTL-18 25 25
50 50
Related Information
4 ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
5 HALF is reduced drive strength.
6 x1 is a single-device load.
7 x2 is a two-device load.
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