Visible to Intel only — GUID: sam1396863898724
Ixiasoft
1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
Visible to Intel only — GUID: sam1396863898724
Ixiasoft
3.1.1.3. DDR2/DDR3 Error Correction Coding Pins
Some DDR2 and DDR3 SDRAM devices support error correction coding (ECC). ECC is a method of detecting and automatically correcting errors in data transmission.
- In 24-bit DDR2 or DDR3 SDRAM, there are eight ECC data pins and 16 data pins.
- Connect the DDR2 and DDR3 SDRAM ECC pins to a separate DQS or DQ group in the MAX® 10 device.
- The memory controller needs additional logic to encode and decode the ECC data.