Visible to Intel only — GUID: mwh1391807012865
Ixiasoft
Visible to Intel only — GUID: mwh1391807012865
Ixiasoft
2.1.1. Intel® FPGA SDK for OpenCL™ Pro Edition-Specific Platform Designer System Components
The board Platform Designer system must export an Avalon®-MM host for controlling OpenCL kernels. It must also export one or more Avalon-MM agent ports that the kernels use as global memory interfaces. The INTELFPGAOCLSDKROOT/ip/board directory of the SDK includes a library that contains SDK-specific Platform Designer system components, where INTELFPGAOCLSDKROOT points to the location of the SDK installation. These components are necessary for implementing features such as Avalon-MM interfaces, organizing programmable banks, cache snooping, and supporting Intel's guaranteed timing closures.
- OpenCL Kernel Clock Generator
The OpenCL™ Kernel Clock Generator is a Platform Designer component that generates a clock output and a clock 2x output for use by the OpenCL kernels. - OpenCL Kernel Interface
The OpenCL™ Kernel Interface is a Platform Designer component that allows the host interface to access and control the OpenCL kernel. - OpenCL Memory Bank Divider
The OpenCL™ Memory Bank Divider is a Platform Designer component that takes an incoming request from the host interface on the Avalon®-MM agent port and routes it to the appropriate bank host port.