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1. Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit Reference Material
3. Intel FPGA SDK for OpenCL Pro Edition Custom Platform Toolkit Archives
4. Document Revision History for Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform
1.3. Custom Platform Automigration for Forward Compatibility
1.4. Creating an Intel® FPGA SDK for OpenCL™ Custom Platform
1.5. Applying for the Intel® FPGA SDK for OpenCL™ Pro Edition Preferred Board Status
1.6. Shipping Recommendations
2.3.1. aocl_mmd_get_offline_info
2.3.2. aocl_mmd_get_info
2.3.3. aocl_mmd_open
2.3.4. aocl_mmd_close
2.3.5. aocl_mmd_read
2.3.6. aocl_mmd_write
2.3.7. aocl_mmd_copy
2.3.8. aocl_mmd_set_interrupt_handler
2.3.9. aocl_mmd_set_device_interrupt_handler
2.3.10. aocl_mmd_set_status_handler
2.3.11. aocl_mmd_yield
2.3.12. aocl_mmd_shared_mem_alloc
2.3.13. aocl_mmd_shared_mem_free
2.3.14. aocl_mmd_program
2.3.15. aocl_mmd_reprogram
2.3.16. aocl_mmd_hostchannel_create
2.3.17. aocl_mmd_hostchannel_destroy
2.3.18. aocl_mmd_hostchannel_get_buffer
2.3.19. aocl_mmd_hostchannel_ack_buffer
2.3.20. aocl_mmd_host_alloc
2.3.21. aocl_mmd_free
2.3.22. aocl_mmd_device_alloc
2.3.23. aocl_mmd_shared_alloc
2.3.24. aocl_mmd_shared_migrate
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2.1.1.3. OpenCL Memory Bank Divider
The OpenCL™ Memory Bank Divider is a Platform Designer component that takes an incoming request from the host interface on the Avalon®-MM agent port and routes it to the appropriate bank host port. This component must reside on the path between the host and the global memory interfaces. In addition, it must reside outside of the path between the kernel and the global memory interfaces.
| Parameter | Description |
|---|---|
| Number of banks | Number of memory banks for each of the global memory types included in your board system. |
| Separate read/write ports | Enable this parameter so that each bank has one port for read operation and one for write operation. |
| Add pipeline stage to output | Enable this parameter to allow for potential timing improvements. |
| Data Width | Width of the data bus to the memory in bits. |
| Address Width (total addressable) | Total number of address bits necessary to address all global memory. |
| Burst size (maximum) | Set to a value equal to interleaved_bytes/(width/8), where interleaved_bytes and width are defined in the interface attribute of the global_mem element in the board_spec.xml file. |
| Maximum Pending Reads | Maximum number of pending read transfers the component can process without asserting a waitrequest signal. Intel® recommended value is 64 if BSP has two global memory banks or fewer and 128 if BSP has four or more global memory banks.
CAUTION:
A high Maximum Pending Reads value causes Platform Designer to insert a deep response FIFO buffer, between the component's host and agent, that consumes a lot of device resources. It also increases the achievable bandwidth between host and memory interfaces.
|
| Split read/write bursts on burst word boundary | Enable splitting of read and write bursts on burst word boundary. Enable this parameter if the Number of banks parameter value is greater than 1, and the burst reads and writes that the host controller sends to the agent port crosses burst word boundary. |
| Signal or Port | Description |
|---|---|
| clk | The bank divider logic uses this clock input. If the IP of your host and memory interfaces have different clocks, ensure that clk clock rate is not slower than the slowest of the two IP clocks. |
| reset | The reset input that connects to the board power-on reset. |
| s | The agent port that connects to the host interface controller. |
| kernel_clk | The kernel_clk output from the OpenCL Kernel Clock Generator drives this clock input. |
| kernel_reset | The kernel_reset output from the OpenCL Kernel Interface drives this reset input. |
| acl_bsp_snoop | Export this Avalon® Streaming (Avalon-ST) source. In the board_spec.xml file, under interfaces, describe only the snoop interface for the default memory (acl_internal_snoop). If you have a heterogeneous memory design, perform these tasks only for the OpenCL Memory Bank Divider component associated with the default memory.
Important: The memory system you build in Platform Designer alters the width of acl_bsp_snoop. You must update the width of the streamsource interface within the channels element in the board_spec.xml file to match the width of acl_bsp_snoop.
Important: In the board_spec.xml file, update the width of the snoop interface (acl_internal_snoop) specified with the streamsource kernel interface within the interfaces element. Updating the width ensures that the global_mem interface entries in board_spec.xml match the characteristics of the bank<N> Avalon-MM hosts from corresponding OpenCL Memory Bank Divider component for the default memory.
|
| acl_bsp_memorg_host | This conduit connects to the acl_bsp_memorg_host interface of the OpenCL Kernel Interface.
Note: Signal present if Number of banks > 1.
. |
| bank1, bank2, ..., bank8 | The number of memory hosts available in the OpenCL Memory Bank Divider depends on the number of memory banks that were included when the unit was instantiated. Connect each bank with each memory interface in the same order as the starting address for the corresponding kernel memory interface specified in the board_spec.xml file. For example, global_mem interface that begins at address 0 must correspond to the memory host in bank1 from the OpenCL Memory Bank Divider. |