Visible to Intel only — GUID: ewa1403029076915
Ixiasoft
1. Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit Reference Material
3. Intel FPGA SDK for OpenCL Pro Edition Custom Platform Toolkit Archives
4. Document Revision History for Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit User Guide
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform Toolkit
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Pro Edition Custom Platform
1.3. Custom Platform Automigration for Forward Compatibility
1.4. Creating an Intel® FPGA SDK for OpenCL™ Custom Platform
1.5. Applying for the Intel® FPGA SDK for OpenCL™ Pro Edition Preferred Board Status
1.6. Shipping Recommendations
2.3.1. aocl_mmd_get_offline_info
2.3.2. aocl_mmd_get_info
2.3.3. aocl_mmd_open
2.3.4. aocl_mmd_close
2.3.5. aocl_mmd_read
2.3.6. aocl_mmd_write
2.3.7. aocl_mmd_copy
2.3.8. aocl_mmd_set_interrupt_handler
2.3.9. aocl_mmd_set_device_interrupt_handler
2.3.10. aocl_mmd_set_status_handler
2.3.11. aocl_mmd_yield
2.3.12. aocl_mmd_shared_mem_alloc
2.3.13. aocl_mmd_shared_mem_free
2.3.14. aocl_mmd_program
2.3.15. aocl_mmd_reprogram
2.3.16. aocl_mmd_hostchannel_create
2.3.17. aocl_mmd_hostchannel_destroy
2.3.18. aocl_mmd_hostchannel_get_buffer
2.3.19. aocl_mmd_hostchannel_ack_buffer
2.3.20. aocl_mmd_host_alloc
2.3.21. aocl_mmd_free
2.3.22. aocl_mmd_device_alloc
2.3.23. aocl_mmd_shared_alloc
2.3.24. aocl_mmd_shared_migrate
Visible to Intel only — GUID: ewa1403029076915
Ixiasoft
2.1.1.1. OpenCL Kernel Clock Generator
The OpenCL™ Kernel Clock Generator is a Platform Designer component that generates a clock output and a clock 2x output for use by the OpenCL kernels. An Avalon®-MM agent interface allows reprogramming of the phase-locked loops (PLLs) and kernel clock status information.
Parameter | Description |
---|---|
REF_CLK_RATE | Frequency of the reference clock that drives the kernel PLL (that is, pll_refclk). |
KERNEL_TARGET_CLOCK_RATE | Frequency that the Intel® Quartus® Prime Pro Edition software attempts to achieve during compilation. Keep this parameter at its default setting. |
Signal or Port | Description |
---|---|
kernel_pll_refclk | The reference clock for the kernel PLL. The frequency of this clock must match the frequency you specify for the REF_CLK_RATE component parameter. |
clk | The clock used for the host control interface. The clock rate of clk can be slow. |
reset | The reset signal that resets the PLL and the control logic. Resetting the PLL disables the kernel clocks temporarily. Connect this reset signal to the power-on reset signal in your system. |
ctrl | The agent port used to connect to the OpenCL host interface and to adjust the frequency based on the OpenCL kernel. |
kernel_clk kernel_clk2x |
The kernel clock and its 2x variant that runs on twice the speed. The kernel_clk2x signal is directly exported from this interface. Because kernel_clk has internal Platform Designer connections, export it using a clock source component. You can also use the clock source to export the kernel reset. In addition, clock all logic at the board Platform Designer system interface with kernel_clk, except for any I/O that you add. |
kernel_pll_locked | (Optional) If the PLL is locked onto the reference clock, the value of this signal is 1. The host interface manages this signal normally; however, this signal is made available in the board Platform Designer system. |