AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683079
Date 7/15/2019
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Document Table of Contents x
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Incremental Block-Based Compilation Tutorial Revision History
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board

1.3.6. Step 6: Optimize Timing-Critical Design Blocks

Follow these steps to optimize the 64-bit counters in blinking_led_8s.sv and blinking_led_16s.sv to improve timing. These changes implement 32-bit addition, rather than 64-bit addition in the counters.
  1. Open blinking_led_8s.sv in a text editor and uncomment the following lines: 
        //reg [31:0] count_msb;
    //reg [31:0] count_lsb;
    //reg [1:0] state=2'b00;
    //always_ff @(posedge fast_clock) begin
    //    fifo_wreq <= 1'b0;	       
    //    case (state)
    //        2'b00: begin
    //            count_lsb <= count_lsb + 1;		  
    //            if (count_lsb[31:0]==32'hFFFFFFFF) begin
    //                state <= 2'b01;	      
    //            end
    //        end
    //        
    //        2'b01: begin
    //            count_lsb <= count_lsb + 1;	   
    //            if (count_lsb[31:0]==32'h064962EC) begin	   	   
    //                count_lsb <= 1;		
    //                value_in <= !value_in;
    //                fifo_wreq <= 1'b1;
    //                state <= 2'b00;
    //            end
    //        end
    //        
    //        default: begin
    //            count_msb <= 0;			
    //            count_lsb <= 0;
    //            state <= 2'b00;
    //        end        	
    //    endcase   
    //end
  2. In blinking_led_8s.sv, comment the following lines and save the changes: 
        reg [63:0] count_in;
    always_ff @(posedge fast_clock) begin
        count_in <= count_in + 1;
        fifo_wreq <= 1'b0;      
        if (count_in==64'd4400440044) begin
            count_in <= 0;
            value_in <= !value_in;	 
            fifo_wreq <= 1'b1;
        end
    end
  3. Open blinking_led_16s.sv and uncomment the following lines: 
        //reg [31:0] count_msb;
    //reg [31:0] count_lsb;
    //reg [1:0] state=2'b00;
    //
    //always_ff @(posedge fast_clock) begin
    //    fifo_wreq <= 1'b0;	       
    //    
    //    case (state)
    //    2'b00: begin
    //        count_lsb <= count_lsb + 1;		  
    //        if (count_lsb[31:0]==32'hFFFFFFFF) begin
    //            state <= 2'b01;	      
    //        end
    //    end
    //    
    //    2'b01: begin
    //       count_lsb <= count_lsb + 1;
    //       if (count_lsb[31:0]==32'hFFFFFFFF) begin	   
    //           state <= 2'b10;	      
    //       end
    //    end	
    //    
    //    2'b10: begin
    //       count_lsb <= count_lsb + 1;	   
    //       if (count_lsb[31:0]==32'h0C92C5D8) begin	   	   
    //           count_lsb <= 1;	      
    //           value_in <= !value_in;
    //           fifo_wreq <= 1'b1;
    //           state <= 2'b00;
    //       end
    //    end
    //    
    //    default: begin
    //        count_msb <= 0;			
    //        count_lsb <= 0;
    //        state <= 2'b00;
    //    end
    //    
    //    endcase
    //end
  4. In blinking_led_16s.sv, comment the following lines and save the changes: 
        reg [63:0] count_in;
    always_ff @(posedge fast_clock) begin
        count_in <= count_in + 1;
        fifo_wreq <= 1'b0;
        if (count_in==64'd8800880088) begin							   
            count_in <= 0;
            value_in <= !value_in;
            fifo_wreq <= 1'b1;
        end	
    end
  5. To compile the design with these changes, click Compile Design on the Compilation Dashboard.
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