AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683079
Date 7/15/2019
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Document Table of Contents x
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Incremental Block-Based Compilation Tutorial Revision History
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board

1.3.2. Step 2: Identify Timing-Critical Design Blocks

Follow these steps to identify the timing-critical design blocks in the Intel® Quartus® Prime Timing Analyzer:
  1. To open the Timing Analyzer, click Tools > Timing Analyzer .
  2. In the Timing Analyzer, on the Tasks pane, double-click Update Timing Netlist to load the final timing netlist generated during the compilation.
    Figure 4.  Timing Analyzer Tasks Pane
  3. To run the report_timing.tcl script to identify any failing paths in the timing-critical design blocks, type the following command in the Console window. If not already visible, click View > Console in the Timing Analyzer to display the Console. The script runs commands to identify any failing paths. 
    source report_timing.tcl

    The tcl script runs the report_timing command, capturing timing for the top 100 paths with the worst slack. The script is also preconfigured to capture timing between specific nodes for some of the design blocks. You analyze timing for these nodes later in this tutorial.

    Figure 5.  Timing Analyzer Report Folders
    Table 2.  Timing Analysis Reports that report_timing.tcl Generates
    Timing Analysis Folder Generated For Timing Reports Show
    inst_big u_big_partition1_top Analysis of top 100 paths with worst slack
    inst_i1 u_blinking_led_i1
    inst_i2 u_blinking_led_i2
    inst_i3 u_blinking_led_i3
    inst_i4 u_blinking_led_i4
    inst_big_path1 u_big_partition1_top Analysis of timing between specific nodes for some partitions
    inst_i1_path1 u_blinking_led_i1
    inst_i2_path1 u_blinking_led_i2
  4. In the inst_big folder, right-click the Slow 900 mV 100C Model report, and then click Generate in All Corners. Repeat this step for the inst_i1, inst_i2, inst_i3, and inst_i4 folders.
  5. View the Multi Corner Summary report that generates under each folder in the Report pane. Reports in red text in the inst_i3 and inst_i4 folders indicate timing-critical design blocks with failing paths.
  6. Open the Multi Corner Summary report in the inst_i3 folder. Check the values in the From Node and To Node fields. Analysis indicates that the failing paths in u_blinking_led_i3 are in the 64-bit counter. This counter counts the number of cycles equivalent to 8s, where each cycle is of 1.818 ns.
    Figure 6. Multi Corner Summary for u_blinking_led_i3
    Note: Due to processor, memory, or OS variations, the slack values in this tutorial are only for reference and may vary from the actual values you observe.
  7. Open the Multi Corner Summary report in the inst_i4 folder. Check the values in the From Node and To Node fields. Analysis indicates that the failing paths in u_blinking_led_i4 are in the 64-bit counter. This counter counts the number of cycles equivalent to 16s, where each cycle is of 1.818 ns.
    Figure 7. Multi Corner Summary for u_blinking_led_i4
    The timing analysis identifies u_blinking_led_i3 and u_blinking_led_i4 as timing-critical design blocks for optimization.
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