F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Control and Status Registers 8. Designing with F-Tile Serial Lite IV Intel® FPGA IP 9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation 4.6. 32-bit Soft CWBIN Counters 4.7. i_stats_snapshot Port
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Control and Status Registers x
7.1. F-Tile Serial Lite IV Intel® FPGA IP Soft CSR
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
8.1. Reset Guidelines 8.2. Error Handling Guidelines 8.3. Analog Parameter Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Control and Status Registers
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP
9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

4.1.4. TX MII Encoder

The TX MII encoder handles the packet transmission from the MAC to the TX PCS.

The data rate determines the TX MII pattern as shown in the following table.

Table 16.  TX MII Encoder Data Pattern
Data Rate Lane Description Pattern
1 Gb to <29 Gb 1 physical lane per 1 lane on GUI IP parameter START and END CW appear in every MII lane
29 Gb to <58 Gb 2 physical lane per 1 lane on GUI IP parameter START and END CW appear once in every two MII lanes
≥58 Gb 4 physical lane per 1 lane on GUI IP parameter START and END CW appear once in every four MII lanes

The following figures demonstrate the data pattern according to data rate.

Table 17.  TX MII Data Pattern for Data Rate of from 1 Gb to Less Than 29 Gb
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 EOP_CW
SOP_CW DATA_2 DATA_10 DATA_18 EOP_CW
SOP_CW DATA_3 DATA_11 DATA_19 EOP_CW
SOP_CW DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 EOP_CW
SOP_CW DATA_6 DATA_14 DATA_22 EOP_CW
SOP_CW DATA_7 DATA_15 DATA_23 EOP_CW
SOP_CW DATA_8 DATA_16 DATA_24 EOP_CW
Table 18.  TX MII Data Pattern for Data Rate of from 29 Gb to Less Than 58 Gb
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 DATA_DUMMY
DATA_DUMMY DATA_2 DATA_10 DATA_18 EOP_CW
SOP_CW DATA_3 DATA_11 DATA_19 DATA_DUMMY
DATA_DUMMY DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 DATA_DUMMY
DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW
SOP_CW DATA_7 DATA_15 DATA_23 DATA_DUMMY
DATA_DUMMY DATA_8 DATA_16 DATA_24 EOP_CW
Table 19.  TX MII Data Pattern for Data Rate of 58 Gb and Higher
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SOP_CW DATA_1 DATA_9 DATA_17 DATA_DUMMY
DATA_DUMMY DATA_2 DATA_10 DATA_18 DATA_DUMMY
DATA_DUMMY DATA_3 DATA_11 DATA_19 DATA_DUMMY
DATA_DUMMY DATA_4 DATA_12 DATA_20 EOP_CW
SOP_CW DATA_5 DATA_13 DATA_21 DATA_DUMMY
DATA_DUMMY DATA_6 DATA_14 DATA_22 DATA_DUMMY
DATA_DUMMY DATA_7 DATA_15 DATA_23 DATA_DUMMY
DATA_DUMMY DATA_8 DATA_16 DATA_24 EOP_CW
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