F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 4/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter Transferring User-defined Information Flow Control 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP
8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

4.1.1. TX MAC Adapter

The TX MAC adapter controls the data transmission to the user logic using the Avalon® streaming interface. This block supports user-defined information transmission and flow control.

Transferring User-defined Information

In Full mode, the IP provides the tx_is_usr_cmd signal that you can use to initiate user-defined information cycle such as XOFF/XON transmission to the user logic. You can initiate the user-defined information transmission cycle by asserting this signal and transfer the information using tx_avs_data along with the assertion of tx_avs_startofpacket and tx_avs_valid signals. The block then deasserts the tx_avs_ready for two cycles.

Note: The user-defined information feature is available only in Full mode.

Flow Control

There are conditions where the TX MAC is not ready to receive data from the user logic such as during link re-alignment process or when there is no data available for transmission from the user logic. To avoid data loss due to these conditions, the IP uses the tx_avs_ready signal to control the data flow from the user logic. The IP deasserts the signal when the following conditions occur:
  • When tx_avs_startofpacket is asserted, tx_avs_ready is deasserted for one clock cycle.
  • When tx_avs_endofpacket is asserted, tx_avs_ready is deasserted for one clock cycle.
  • When any paired CWs is asserted tx_avs_ready is deasserted for two clock cycles.
  • When RS-FEC alignment marker insertion occurs at the custom PCS interface, tx_avs_ready is deasserted for four clock cycles.
  • Every 17 Ethernet core clock cycles in PAM4 modulation mode and every 33 Ethernet core clock cycles in NRZ modulation mode. The tx_avs_ready is deasserted for one clock cycle.
  • When user logic deasserts tx_avs_valid during no data transmission.
The following timing diagrams are examples of TX MAC adapter using tx_avs_ready for data flow control.
Figure 8. Flow Control with tx_avs_valid Deassertion and START/END Paired CWs
Figure 9. Flow Control with Alignment Marker Insertion
Figure 10. Flow Control with START/END Paired CWs Coincide with Alignment Marker Insertion
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