100G Interlaken Design Example User Guide

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ID 683071
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 100G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 100G Interlaken Design Example User Guide

2.5. Interface Signals

Table 2.  Arria 10 100G Interlaken IP Core Hardware Example Design Signals

Port Name

Direction

Width (Bits)

Description

clk50

Input

1

System clock input. Clock frequency must be 50 MHz.

pll_ref_clk

Input

1

Transceiver reference clock. Drives the RX CDR PLL.

rx_pin

Input

Number of lanes

Receiver SERDES data pin.

tx_pin

Output

Number of lanes

Transmit SERDES data pin.

sys_pll_reset_n Input 1 System reset.
Level Two Title