F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Download PDF
ID 683069
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.3. Interface Signals

Table 6.  Design Example Interface Signals
Port Name Direction Width (Bits) Description
mgmt_clk Input 1 System clock input. Clock frequency must be 100 MHz.
pll_ref_clk Input 1 F-tile Transceiver reference clock for PMA. Drives the RX CDR PLL.

The default clock frequency is 156.25MHz for the design example. You can modify this frequency to match the settings in F-Tile Reference and System PLL Clocks Intel FPGA IP and F-tile Interlaken Intel FPGA IP.

systempll_ref_clk Input 1 F-tile Transceiver reference clock for SystemPLL.

The default clock frequency is 156.25MHz for the design example. You can modify this frequency to match the settings in F-Tile Reference and System PLL Clocks Intel FPGA IP and F-tile Interlaken Intel FPGA IP.

rx_pin Input Number of lanes Receiver SERDES data pin.
tx_pin Output Number of lanes Transmit SERDES data pin.
rx_pin_n 3 Input Number of lanes Receiver SERDES data pin.
tx_pin_n 3 Output Number of lanes Transmit SERDES data pin.
mac_clk_pll_ref 3 Input 1 In design example, the iopll_mac_clk instance uses this signal to generate the 395.833333MHz MAC clock that drives the mac_clkin input port of F-tile Interlaken Intel FPGA IP.

The mac_clk_pll_ref frequency is 156.25MHz for default design example. You can update to match the iopll_mac_clk settings. This signal is only available in PAM4 mode device variations.

tx_fc_clk 4 Output 1 Output reference clock to a downstream out-of-band RX block. Clocks the fc_data and fc_sync signals. You must connect this signal to a device pin.
tx_fc_data 4 Output 1 Output serial data pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
tx_fc_sync 4 Output 1 Output sync control pin to a downstream out-of-band RX block. You must connect this signal to a device pin.
rx_fc_clk 4 Input 1 Input reference clock from an upstream out-of-band TX block. This signal clocks the fc_data and fc_sync signals. You must connect this signal to a device pin.
rx_fc_data 4 Input 1 Input serial data pin from an upstream out-of-band TX block. You must connect this signal to a device pin.
rx_fc_sync 4 Input 1 Input sync control pin from an upstream out-of-band TX block. You must connect this signal to a device pin.
usr_pb_reset_n Input 1 System reset.

3 Only available in PAM4 variants.
4 In the Intel® Quartus® Prime Static Timing Analysis report, this port appears as an unconstrained output port and should not affect your functionality when out-of-band flow control is not required.
Level Two Title