F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Download PDF
ID 683069
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.26 22.3 5.0.0
  • Updated the development kit device part numbers in section: Generating the Design.
  • Updated the Figure: Directory Structure.
  • Updated the steps in section: Compiling and Configuring the Hardware Design Example.
  • Added the external serial loopback support for FHT PMA.
  • Updated the section: Interface Signals with:
    • pll_ref_clk signal description
    • New signals:
      • systempll_ref_clk
      • tx_fc_clk
      • tx_fc_data
      • tx_fc_sync
      • rx_fc_clk
      • rx_fc_data
      • rx_fc_sync
2022.06.21 22.2 4.1.0
  • Added the FHT PMA support for PAM4 variants.
  • Updated commands in section: Testing the Hardware Design Example.
2022.03.28 22.1 4.0.0
  • Added support for the Interlaken Look-aside mode for all variants.
  • Removed support for the ModelSim* SE simulator.
2022.01.14 21.4 3.1.0
  • Added support for the Cadence* Xcelium* simulator.
  • Added support for the Interlaken Look-aside mode for three variants:
    • 6 x 53.125G
    • 12 x 12.5G
    • 12 x 25.78125G
  • Added hardware support for the F-tile Interlaken Intel® FPGA IP Design Example.
2021.10.04 21.3 3.0.0
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the supported simulator list in section: Hardware and Software Requirements.
  • Added new reset registers in section: Register Map.
2021.06.21 21.2 2.0.0 Initial release.
Level Two Title