Visible to Intel only — GUID: elc1689124475825
Ixiasoft
1.1. 25G Intel® FPGA IP Ethernet v20.1.0
1.2. 25G Ethernet Intel® FPGA IP v20.0.0
1.3. 25G Ethernet Intel® FPGA IP v19.5.0
1.4. 25G Ethernet Intel® FPGA IP v19.4.1
1.5. 25G Ethernet Intel® FPGA IP v19.4.0
1.6. 25G Ethernet Intel® FPGA IP v19.3.0
1.7. 25G Ethernet Intel® FPGA IP v19.2.0
1.8. 25G Ethernet Intel® FPGA IP v19.1
1.9. 25G Ethernet Intel® FPGA IP v18.1
1.10. 25G Ethernet Intel® FPGA IP v18.0
1.11. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
1.12. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
2.1. 25G Ethernet Intel® FPGA IP v19.4.1
2.2. 25G Ethernet Intel® FPGA IP v19.4.0
2.3. 25G Ethernet Intel® FPGA IP v19.1
2.4. 25G Ethernet IP Core v17.0
2.5. 25G Ethernet IP Core v16.1
2.6. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive
2.7. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
Visible to Intel only — GUID: elc1689124475825
Ixiasoft
1.1. 25G Intel® FPGA IP Ethernet v20.1.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
22.4 | Fixed i_csr_rst_n, i_tx_rst_n, and i_rx__rst_n input signals that affect interconnection in the Platform Designer. | — |