20.4 |
Length checking update on VLAN frames:
- In previous versions of 25G Ethernet Intel® FPGA IP, oversized frame error is asserted when the following conditions are met:
- VLAN
- VLAN detection is enabled.
- The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 4 octets.
- SVLAN
- SVLAN detection is enabled.
- The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 8 octets.
- In this version, the IP is updated to correct this behavior.
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Updated the Avalon® memory-mapped interface access to the status_* interface to prevent Avalon® memory-mapped timeout during reads to non-existent addresses:
- In previous versions of 25G Ethernet Intel® FPGA IP, Avalon® memory-mapped interface reads to non-existent addresses on the status_* interface would assert status_waitrequest until the Avalon® memory-mapped master’s request times out. The issue has now been fixed to not hold waitrequest when a non-existent address is accessed.
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RS-FEC enabled variants now support 100% throughput. |
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