25G Ethernet Intel® FPGA IP Release Notes

ID 683067
Date 8/01/2023
Public

1.4. 25G Ethernet Intel® FPGA IP v19.4.1

Table 4.  v19.4.1 2020.12.14
Intel® Quartus® Prime Version Description Impact
20.4
Length checking update on VLAN frames:
  • In previous versions of 25G Ethernet Intel® FPGA IP, oversized frame error is asserted when the following conditions are met:
    1. VLAN
      1. VLAN detection is enabled.
      2. The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 4 octets.
    2. SVLAN
      1. SVLAN detection is enabled.
      2. The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 8 octets.
  • In this version, the IP is updated to correct this behavior.
Updated the Avalon® memory-mapped interface access to the status_* interface to prevent Avalon® memory-mapped timeout during reads to non-existent addresses:
  • In previous versions of 25G Ethernet Intel® FPGA IP, Avalon® memory-mapped interface reads to non-existent addresses on the status_* interface would assert status_waitrequest until the Avalon® memory-mapped master’s request times out. The issue has now been fixed to not hold waitrequest when a non-existent address is accessed.
RS-FEC enabled variants now support 100% throughput.