P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683059
Date 2/01/2023
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Advanced Features 4. Interfaces 5. Parameters 6. Testbench 7. Troubleshooting/Debugging 8. P-tile Avalon® Streaming Intel FPGA IP for PCI Express* User Guide Archives 9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations F. Bifurcated Endpoint Support for Independent Warm Resets G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Architecture 2.2. Functional Description
2.1. Architecture x
2.1.1. Clock Domains 2.1.2. Refclk 2.1.3. Reset
2.1.3. Reset x
2.1.3.1. Independent PERST
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview
3. Advanced Features x
3.1. PCIe* Port Bifurcation and PHY Channel Mapping 3.2. Virtualization Support 3.3. TLP Bypass Mode
3.2. Virtualization Support x
3.2.1. SR-IOV Support 3.2.2. VirtIO Support
3.2.1. SR-IOV Support x
3.2.1.1. SR-IOV Supported Features List 3.2.1.2. Implementation 3.2.1.3. VF to PF Mapping 3.2.1.4. Function Level Reset (FLR)
3.2.1.2. Implementation x
3.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
3.2.2. VirtIO Support x
3.2.2.1. VirtIO Supported Features List 3.2.2.2. Overview 3.2.2.3. Parameters 3.2.2.4. VirtIO PCI Configuration Access Interface 3.2.2.5. Registers
3.2.2.5. Registers x
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035 ) 3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
3.3. TLP Bypass Mode x
3.3.1. Overview 3.3.2. Register Settings for the TLP Bypass Mode 3.3.3. User Avalon® -MM Interface 3.3.4. Avalon® -ST Interface
3.3.2. Register Settings for the TLP Bypass Mode x
3.3.2.1. TLPBYPASS_ERR_EN (Address 0x104194) 3.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x104190)
3.3.4. Avalon® -ST Interface x
3.3.4.1. Configuration TLP 3.3.4.2. Transmit Interface 3.3.4.3. Receive Interface 3.3.4.4. Malformed TLP 3.3.4.5. ECRC
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. Avalon-ST Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Error Interface 4.8. Hot Plug Interface (RP Only) 4.9. Power Management Interface 4.10. Configuration Output Interface 4.11. Configuration Intercept Interface (EP Only) 4.12. Hard IP Reconfiguration Interface 4.13. PHY Reconfiguration Interface 4.14. Page Request Service (PRS) Interface (EP Only)
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Resets
4.2.2. Resets x
4.2.2.1. Interface Reset Signals 4.2.2.2. Function-Level Reset (FLR) Interface (EP Only)
4.4. Avalon-ST Interface x
4.4.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 4.4.2. Avalon® -ST RX Interface 4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior 4.4.4. RX Flow Control Interface 4.4.5. Avalon® -ST TX Interface 4.4.6. Avalon® -ST TX Interface tx_st_ready Behavior 4.4.7. TX Flow Control Interface 4.4.8. Tag Allocation
4.4.8. Tag Allocation x
4.4.8.1. Completion Buffer Size
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.7. Error Interface x
4.7.1. Completion Timeout Interface 4.7.2. VF Error Flags Interface
4.12. Hard IP Reconfiguration Interface x
4.12.1. Address Map for the User Avalon-MM Interface 4.12.2. Configuration Registers Access
4.12.1. Address Map for the User Avalon-MM Interface x
4.12.1.1. User Avalon-MM Control Register (Offset 0x104068)
4.12.2. Configuration Registers Access x
4.12.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.12.2.2. Using the Debug Register Interface Access (Dword Access)
5. Parameters x
5.1. Top-Level Settings 5.2. Core Parameters
5.2. Core Parameters x
5.2.1. Avalon® Parameters 5.2.2. Base Address Registers 5.2.3. PCI Express and PCI Capabilities Parameters 5.2.4. Device Identification Registers 5.2.5. Configuration, Debug and Extension Options
5.2.3. PCI Express and PCI Capabilities Parameters x
5.2.3.1. Device Capabilities 5.2.3.2. VirtIO Parameters 5.2.3.3. Link Capabilities 5.2.3.4. Legacy Interrupt Pin Register 5.2.3.5. MSI Capabilities 5.2.3.6. MSI-X Capabilities 5.2.3.7. Slot Capabilities 5.2.3.8. Latency Tolerance Reporting (LTR) 5.2.3.9. Process Address Space ID (PASID) 5.2.3.10. Device Serial Number Capability 5.2.3.11. Page Request Service (PRS) 5.2.3.12. Access Control Service (ACS) Capabilities 5.2.3.13. Power Management 5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers 5.2.3.15. TLP Processing Hints (TPH) 5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.1. Device Capabilities x
5.2.3.1.1. Multifunction and SR-IOV System Parameters
6. Testbench x
6.1. Endpoint Testbench 6.2. Test Driver Module 6.3. Root Port BFM
6.3. Root Port BFM x
6.3.1. BFM Memory Map 6.3.2. Configuration Space Bus and Device Numbering 6.3.3. Configuration of Root Port and Endpoint 6.3.4. Issuing Read and Write Transactions to the Application Layer 6.3.5. BFM Procedures and Functions
6.3.5. BFM Procedures and Functions x
6.3.5.1. ebfm_barwr Procedure 6.3.5.2. ebfm_barwr_imm Procedure 6.3.5.3. ebfm_barrd_wait Procedure 6.3.5.4. ebfm_barrd_nowt Procedure 6.3.5.5. ebfm_cfgwr_imm_wait Procedure 6.3.5.6. ebfm_cfgwr_imm_nowt Procedure 6.3.5.7. ebfm_cfgrd_wait Procedure 6.3.5.8. ebfm_cfgrd_nowt Procedure 6.3.5.9. BFM Configuration Procedures 6.3.5.10. BFM Shared Memory Access Procedures 6.3.5.11. BFM Log and Message Procedures 6.3.5.12. Verilog HDL Formatting Functions
6.3.5.9. BFM Configuration Procedures x
6.3.5.9.1. ebfm_cfg_rp_ep Procedure 6.3.5.9.2. ebfm_cfg_decode_bar Procedure
6.3.5.10. BFM Shared Memory Access Procedures x
6.3.5.10.1. Shared Memory Constants 6.3.5.10.2. shmem_write Task 6.3.5.10.3. shmem_read Function 6.3.5.10.4. shmem_display Verilog HDL Function 6.3.5.10.5. shmem_fill Procedure 6.3.5.10.6. shmem_chk_ok Function
6.3.5.11. BFM Log and Message Procedures x
6.3.5.11.1. ebfm_display Verilog HDL Function 6.3.5.11.2. ebfm_log_stop_sim Verilog HDL Function 6.3.5.11.3. ebfm_log_set_suppressed_msg_mask Task 6.3.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 6.3.5.11.5. ebfm_log_open Verilog HDL Function 6.3.5.11.6. ebfm_log_close Verilog HDL Function
6.3.5.12. Verilog HDL Formatting Functions x
6.3.5.12.1. himage1 6.3.5.12.2. himage2 6.3.5.12.3. himage4 6.3.5.12.4. himage8 6.3.5.12.5. himage16 6.3.5.12.6. dimage1 6.3.5.12.7. dimage2 6.3.5.12.8. dimage3 6.3.5.12.9. dimage4 6.3.5.12.10. dimage5 6.3.5.12.11. dimage6 6.3.5.12.12. dimage7
7. Troubleshooting/Debugging x
7.1. Hardware 7.2. Debug Toolkit
7.1. Hardware x
7.1.1. Debugging Link Training Issues 7.1.2. Debugging Data Transfer and Performance Issues
7.1.1. Debugging Link Training Issues x
7.1.1.1. Generic Tools and Utilities 7.1.1.2. Signal Tap II Logic Analyzer 7.1.1.3. Additional Debug Tools
7.1.2. Debugging Data Transfer and Performance Issues x
7.1.2.1. Advanced Error Reporting (AER) 7.1.2.2. Second-Level Debug Tools
7.2. Debug Toolkit x
7.2.1. Overview 7.2.2. Enabling the P-Tile Debug Toolkit 7.2.3. Launching the P-Tile Debug Toolkit 7.2.4. Using the P-Tile Debug Toolkit 7.2.5. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations x
E.1. Overview E.2. Generate the PCIe PIO Example Design E.3. Integrate Avery BFMs (Root Complex) E.4. Configure the Avery BFM and Update the Simulation Script E.5. Compile and Simulate E.6. View the Results
E.2. Generate the PCIe PIO Example Design x
E.2.1. Avalon® -ST PCIe PIO Example Design
F. Bifurcated Endpoint Support for Independent Warm Resets x
F.1. PCI Express Resets F.2. P-tile PCIe Design Constraints
F.2. P-tile PCIe Design Constraints x
F.2.1. P-tile Dual-Endpoint System Configurations
G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express x
G.1. Margin Masks Overview G.2. Nx5 Testing Efficiency G.3. Debug Toolkit Margin Methodology
G.2. Nx5 Testing Efficiency x
G.2.1. First Time Testing G.2.2. Spot Check Testing
G.3. Debug Toolkit Margin Methodology x
G.3.1. Debug Toolkit (DTK) Testing Process G.3.2. DTK Margin Evaluation Based on Margin Mask Values
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Testbench
7. Troubleshooting/Debugging
8. P-tile Avalon® Streaming Intel FPGA IP for PCI Express* User Guide Archives
9. Document Revision History for the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
E. Using the Avery BFM for Intel P-Tile PCI Express Gen4 x16 Simulations
F. Bifurcated Endpoint Support for Independent Warm Resets
G. Margin Masks for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express

4.10. Configuration Output Interface

The Transaction Layer configuration output (tl_cfg) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.

Note: User application logic should not use this interface during TLP Bypass mode as the information on this interface is not valid in that mode.
Table 73.  Configuration Output Interface
Signal Name Direction Description Clock Domain EP/RP/BP
tl_cfg_ctl_o[15:0] O Multiplexed data output from the register specified by tl_cfg_add_o[4:0]. The detailed information for each field in this bus is defined in the following table. coreclkout_hip EP/RP/BP
tl_cfg_add_o[4:0] O This address bus contains the index indicating which Configuration Space register information is being driven onto the tl_cfg_ctl_o[15:0] bits. coreclkout_hip EP/RP/BP

x16/x8: tl_cfg_func_o[2:0]

x4: NA

 O Specifies the function whose Configuration Space register values are being driven out on tl_cfg_ctl_o[15:0].
  • 3'b000: Physical Function 0 (PF0)
  • 3'b001: PF1

and so on

 coreclkout_hip EP/RP/BP

The table below provides the tl_cfg_add_o[4:0] to tl_cfg_ctl_o[15:0] mapping.

Table 74.  Multiplexed Configuration Information Available on tl_cfg_ctl
tl_cfg_add_o[4:0] tl_cfg_ctl_o[15:8] tl_cfg_ctl_o[7:0]
5'h00

[15]: memory space enable

[14]: IDO completion enable

[13]: perr_en

[12]: serr_en

[11]: fatal_err_rpt_en

[10]: nonfatal_err_rpt_en

[9]: corr_err_rpt_en

[8]: unsupported_req_rpt_en

Device control:

[7]: bus master enable

[6]: extended tag enable

[5:3]: maximum read request size

[2:0]: maximum payload size
5'h01

[15]: IDO request enable

[14]: No Snoop enable

[13]: Relaxed Ordering enable

[12:8]: Device number

 bus number
5'h02

[15]: pm_no_soft_rst

[14]: RCB control

[13]: Interrupt Request (IRQ) disable

[12:8]: PCIe Capability IRQ message number

[7:5]: reserved

[4]: system power control

[3:2]: system attention indicator control

[1:0]: system power indicator control
5'h03 Number of VFs [15:0]
5'h04

[15]: reserved

[14]: AtomicOP Egress Block field (cfg_atomic_egress_block)

[13:9]: ATS Smallest Translation Unit (STU)[4:0]

[8]: ATS cache enable

[7]: ARI forward enable

[6]: Atomic request enable

[5:3]: TPH ST mode

[2:1]: TPH enable

[0]: VF enable
5'h05
[15:12]: auto negotiation link speed. Link speed encoding values are:
  • Gen1 : 0x1
  • Gen2 : 0x2
  • Gen3 : 0x4
  • Gen4 : 0x8

[11:1]: Index of Start VF [10:0]

[0]: reserved

  
5'h06 MSI Address [15:0]
5'h07 MSI Address [31:16]
5'h08 MSI Address [47:32]
5'h09 MSI Address [63:48]
5'h0A MSI Mask [15:0]
5'h0B MSI Mask [31:16]
5'h0C

[15]: cfg_send_f_err

[14]: cfg_send_nf_err

[13]: cfg_send_cor_err

[12:8]: AER IRQ message number

[7]: Enable extended message data for MSI (cfg_msi_ext_data_en)

[6]: MSI-X func mask

[5]: MSI-X enable

[4:2]: Multiple MSI enable

[1]: 64-bit MSI

[0]: MSI enable
5'h0D MSI Data [15:0]  
5'h0E AER uncorrectable error mask [15:0]
5'h0F AER uncorrectable error mask [31:16]
5'h10 AER correctable error mask [15:0]
5'h11 AER correctable error mask [31:16]
5'h12 AER uncorrectable error severity [15:0]
5'h13 AER uncorrectable error severity [31:16]
5'h14 [15:8]: ACS Egress Control Register (cfg_acs_egress_ctrl_vec)

[7]: ACS function group enable (cfg_acs_func_grp_en)

[6]: ACS direct translated P2P enable (cfg_acs_p2p_direct_tranl_en)

[5]: ACS P2P egress control enable (cfg_acs_egress_ctrl_en)

[4]: ACS upstream forwarding enable (cfg_acs_up_forward_en)

[3]: ACS P2P completion redirect enable (cfg_acs_p2p_compl_redirect_en)

[2]: ACS P2P request redirect enable (cfg_acs_p2p_req_redirect_en)

[1]: ACS translation blocking enable (cfg_acs_at_blocking_en)

[0]: ACS source validation enable (RP) (cfg_acs_validation_en)

5'h15

[15:13]: reserved

[12]: PRS_RESP_FAILURE (cfg_prs_response_failure)

[11]: PRS_UPRGI (cfg_prs_uprgi)

[10]: PRS_STOPPED (cfg_prs_stopped)

[9]: PRS_RESET (cfg_prs_reset)

[8]: PRS_ENABLE (cfg_prs_enable)

[7:3]: reserved

[2:0]: ARI function group (cfg_ari_func_grp)

5'h16 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [15:0]  
5'h17 PRS_OUTSTANDING_ALLOCATION (cfg_prs_outstanding_allocation) [31:16]  
5'h18

[15:10]: reserved

[9]: Disable autonomous generation of LTR clear message (cfg_disable_ltr_clr_msg)

[8]: LTR mechanism enable (cfg_ltr_m_en)

[7]: Infinite credits for Posted header

[6]: Infinite credits for Posted data

[5]: Infinite credits for Completion header

[4]: Infinite credits for Completion data

[3]: End-end TLP prefix blocking (cfg_end2end_tlp_pfx_blck)

[2]: PASID enable (cfg_pf_pasid_en)

[1]: Execute permission enable (cfg_pf_passid_execute_perm_en )

[0]: Privileged mode enable (cfg_pf_passid_priv_mode_en)

5'h19

[15:9]: reserved

[8]: Slot control attention button pressed enable (cfg_atten_button_pressed_en)

[7]: Slot control power fault detect enable (cfg_pwr_fault_det_en)

[6]: Slot control MRL sensor changed enable (cfg_mrl_sensor_chged_en)

[5]: Slot control presence detect changed enable (cfg_pre_det_chged_en)

[4]: Slot control hot plug interrupt enable (cfg_hp_int_en)

[3]: Slot control command completed interrupt enable (cfg_cmd_cpled_int_en)

[2]: Slot control DLL state change enable (cfg_dll_state_change_en)

[1]: Slot control accessed (cfg_hp_slot_ctrl_access)

[0]: PF’s SERR# enable (cfg_br_ctrl_serren)

5'h1A LTR maximum snoop latency register (cfg_ltr_max_latency[15:0])  
5'h1B LTR maximum no-snoop latency register (cfg_ltr_max_latency[31:16])  
5'h1C [15:8]: enabled Traffic Classes (TCs) (cfg_tc_enable[7:0])

[5:0]: auto negotiation link width

6’h01 = x1

6’h02 = x2

6’h04 = x4

6’h08 = x8

6’h10 = x16
5'h1D MSI Data[31:16]
5'h1E N/A
5'h1F N/A
Note:

The information on the Configuration Output (tl_cfg) bus is time-division multiplexed (TDM).

  • When tl_cfg_func[2:0] = 3'b000, tl_cfg_ctl[31:0] drive out the PF0 Configuration Space register values.
  • Then, tl_cfg_func[2:0] are incremented to 3'b001.
  • When tl_cfg_func[2:0] = 3'b001, tl_cfg_ctl[31:0] drive out the PF1 Configuration Space register values.
  • This pattern repeats to cover all enabled PFs.
Figure 39. Configuration Output Interface Timing Diagram
Note: The P-Tile IP for PCIe provides a data link layer timer update output. Details on this signal are in the table below. When this signal asserts, you can sample the tl_cfg_ctl_o bus to see the new link speed, link width or max payload size and update the Replay/Ack-Nak timers accordingly.
Table 75.  Data Link Layer Timer Update Signal
Signal Name Direction Description Clock Domain EP/RP/BP
dl_timer_update_o O

Active high pulse that asserts whenever the current link speed, link width, or max payload size changes.

When any of these parameters changes, the IP's internal Replay/Ack-Nak timers default back to their internally calculated PCIe tables.

To override these default values, reprogram the Port Logic register when these events occur.

coreclkout_hip EP/RP/BP
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