Intel® High Level Synthesis Compiler Standard Edition: Getting Started Guide

ID 683053
Date 3/26/2020
Public

2.2. Running a High Level Synthesis (HLS) Design Example (Windows)

To run an HLS design example on Windows systems:

  1. Start a terminal session and initialize the Intel® HLS Compiler environment.
    For instructions how to initialize the environment, see Initializing the Intel HLS Compiler Standard Edition Environment.
  2. Navigate to the <quartus_installdir>\hls\examples\<design_example_name> directory, where <quartus_installdir> is the directory where you installed Intel® Quartus® Prime software.
    For example, C:\intelFPGA_standard\22.1 .
  3. Run the build.bat test-x86-64. This command compiles the C++ source code to an x86-64 binary executable. Then, run the generated executable on your CPU.
    Expected outcome after you run the build.bat test-x86-64 command:
    • The console displays the command it uses to generate the binary. For example, i++ -march=x86-64 -o test-x86-64 <source_files> .
    • The HLS compiler creates an executable file (for example, test-x86-64.exe) in the current working directory.
    • The console displays the output of the executable to signify a successful execution.
    C:\intelFPGA_standard\22.1\hls\examples\QRD>build.bat test-x86-64
    i++ --fpc --fp-relaxed -march=x86-64 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-x86-64.exe
    Run test-x86-64.exe to execute the test.
  4. Run the build.bat test-fpga command. The command compiles the C++ source code to a hardware executable and then runs a simulation of the generated HDL.
    Expected outcome after you run the build.bat test-fpga command:
    • The console displays the command it uses to generate the testbench binary and the contents of the project directory. For example, i++ -march="<FPGA_family_or_part_number>" <source_files> -o test-fpga.
    • The HLS compiler creates a .prj directory (for example, test-fpga.prj) in the current working directory.
    • The console displays the output of the executable to signify a successful execution.
    C:\intelFPGA_standard\22.1\hls\examples\QRD>build.bat test-fpga
    i++ --fpc --fp-relaxed -march=Arria10 MGS.cpp QRD_Testbench.cpp TestbenchHelpers.cpp -o test-fpga.exe
    Run test-fpga.exe to execute the test.