Intel® High Level Synthesis Compiler Standard Edition: Getting Started Guide

ID 683053
Date 3/26/2020
Public
Document Table of Contents

2. High Level Synthesis (HLS) Design Examples and Tutorials

The Intel® High Level Synthesis (HLS) Compiler Standard Edition includes design examples and tutorials to provide you with example components and demonstrate ways to model or code your components to get the best results from the Intel® HLS Compiler for your design.

High Level Synthesis Design Examples

The high level synthesis (HLS) design examples give you a quick way to see how various algorithms can be effectively implemented to get the best results from the Intel® HLS Compiler.

You can find the HLS design examples in the following location:
<quartus_installdir>/hls/examples/<design_example_name>

Where <quartus_installdir> is the directory where you installed the Intel® Quartus® Prime Design Suite. For example, /home/<username>/intelFPGA_standard/22.1 or C:\intelFPGA_standard\22.1 .

Table 2.  HLS design examples
Focus area Name Description
Linear algebra QRD Uses the Modified Gram-Schmidt algorithm for QR factorization of a matrix.
Signal processing interp_decim_filter Implements a simple and efficient interpolation/decimation filter.
Simple design counter Implements a simple and efficient 32-bit counter component.
Video processing YUV2RGB Implements a basic YUV422 to RGB888 color space conversion.
Video processing image_downsample Implements an image downsampling algorithm to scale an image to a smaller size using bilinear interpolation.

HLS Design Tutorials

The HLS design tutorials show you important HLS-specific programming concepts as well demonstrating good coding practices.

Each tutorial has a README file that gives you details about what the tutorial covers and instructions on how to run the tutorial.

Table 3.  Arbitrary precision datatypes design tutorials
Name Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/ac_datatypes
ac_fixed_constructor Demonstrates the use of the ac_fixed constructor where you can get a better QoR by using minor variations in coding style.
ac_fixed_math_library Demonstrates the use of the Intel® HLS Compiler ac_fixed_math fixed point math library functions.
ac_int_basic_ops Demonstrates the operators available for the ac_int class.
ac_int_overflow Demonstrates the usage of the DEBUG_AC_INT_WARNING and DEBUG_AC_INT_ERROR keywords to help detect overflow during emulation runtime.
Table 4.  Component memories design tutorials
Name Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/component_memories
bank_bits Demonstrates how to control component internal memory architecture for parallel memory access by enforcing which address bits are used for banking.
depth_wise_merge Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a depth equal to the sum of the depths of the two original memories.
static_var_init Demonstrates the hls_init_on_power and hls_init_on_reset flags for static variables and their impact on area and latency.
width_wise_merge Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a width equal to the sum of the widths of the two original memories.
Table 5.  Interfaces design tutorials
Name Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/interfaces
overview Demonstrates the effects on quality-of-results (QoR) of choosing different component interfaces even when the component algorithm remains the same.
explicit_streams_buffer

Demonstrates how to use explicit stream_in and stream_out interfaces in the component and testbench.

explicit_streams_packets_d ready_valid Demonstrates how to use the usesPackets, usesValid, and usesReady stream template parameters.
mm_master_testbench_operators Demonstrates how to invoke a component at different indicies of an Avalon Memory Mapped (MM) Master (mm_master class) interface.
mm_slaves Demonstrates how to create Avalon-MM Slave interfaces (slave registers and slave memories).
multiple_stream_call_sites Demonstrates the benefits of using multiple stream call sites.
pointer_mm_master Demonstrates how to create Avalon-MM Master interfaces and control their parameters.
stable_arguments Demonstrates how to use the stable attribute for unchanging arguments to improve resource utilization.
Table 6.  Best practices design tutorials
Name Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/best_practices
const_global Demonstrates the performance and resource utilization improvements of using const qualified global variables.
floating_point_ops Demonstrates the impact of --fpc and --fp-relaxed flags in i++ on floating point operations using a 32-tap finite impulse response (FIR) filter design that is optimized for throughput.
integer_promotion Demonstrates how integer promotion rules can influence the behavior of a C or C++ program.
loop_memory_dependency Demonstrates breaking loop carried dependencies using the ivdep pragma.
parameter_aliasing

Demonstrates the use of the restrict keyword on component arguments.

resource_sharing_filter Demonstrates an optimized-for-area variant of a 32-tap finite impulse response (FIR) filter design
shift_register Demonstrates the recommended coding style for implementing shift registers.
single_vs_double_precision_math Demonstrates the effect of using single precision literals and functions instead of double precision literals and functions.
struct_interface Demonstrates how to use ac_int to implement interfaces with no padding bits.
swap_vs_copy Demonstrates the impact of using deep copying with registers on the performance and resource utilization of a component design.
Table 7.  Usability design tutorials
Name Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/usability
compiler_interoperability (Linux only) Demonstrates how to use testbench code compiled with GCC along with code compiled by the i++ command.
enqueue_call Demonstrates how to run components asynchronously and exercise their pipeline performance in the test bench using enqueue functionality.

qsys_2xclock

Demonstrates the recommended clock and reset generation for a component with a clock2x input.

qsys_stitching

Demonstrates how to combine multiple components to function as a single cohesive design.