Visible to Intel only — GUID: mcn1395814775696
Ixiasoft
Visible to Intel only — GUID: mcn1395814775696
Ixiasoft
2.3.11.1. Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters.
The duty cycle setting is achieved by a low and high time-count setting for the post-scale counters. To determine the duty cycle choices, the Intel® Quartus® Prime software uses the frequency input and the required multiply or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise nonoverlapping clocks.