Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Public
Document Table of Contents

6.1.6. Dynamic Phase Configuration Parameter Settings

The parameter settings to enable the dynamic phase configuration feature are located on the PLL Reconfiguration page of the Avalon ALTPLL Intel® FPGA IP parameter editor.

Table 20.  Dynamic Phase Configuration Parameter Editor Settings
Parameter Value Description
Create optional inputs for dynamic phase reconfiguration On or Off

Turn on this option to enable the dynamic phase configuration feature. The following ports are created:

  • phasecounterselect[2..0]
  • phaseupdown
  • phasestep
  • scanclk
  • phasedone
Enable phase shift step resolution edit On or Off

Turn on this option to modify the value for Phase shift step resolution(ps) for each individual PLL output clock on the Output Clocks page.

By default, the finest phase shift resolution value is 1/8 of the VCO period. If the VCO frequency is at the lower end of the supported VCO range, the phase shift resolution might be larger than preferred for your design. Use this option to fine tune the phase shift step resolution.