Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Quartus® Prime Programmer User Guide 2. Using the Quartus® Prime Programmer 3. Using the HPS Flash Programmer A. Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Quartus® Prime Pro Edition User Guides
1. Quartus® Prime Programmer User Guide x
1.1. Generating Primary Device Programming Files 1.2. Generating Secondary Programming Files 1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices 1.4. Enabling Bitstream Encryption or Compression for Arria® 10 and Cyclone® 10 GX Devices 1.5. Generating Programming Files for Partial Reconfiguration 1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 1.7. Scripting Support 1.8. Generating Programming Files Revision History
1.1. Generating Primary Device Programming Files x
1.1.1. Specifying Voltage Regulator Options
1.2. Generating Secondary Programming Files x
1.2.1. Generating Secondary Programming Files (Programming File Generator) 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 1.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
1.2.1. Generating Secondary Programming Files (Programming File Generator) x
1.2.1.1. Configuration Modes (Programming File Generator) 1.2.1.2. Secondary Programming Files (Programming File Generator)
1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
1.2.2.1. Secondary Programming Files (Convert Programming Files) 1.2.2.2. Configuration Modes (Convert Programming Files) 1.2.2.3. Debugging the Configuration (Convert Programming Files)
1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices x
1.3.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 1.3.3. Enabling Bitstream Encryption (Programming File Generator)
1.5. Generating Programming Files for Partial Reconfiguration x
1.5.1. Generating PR Bitstream Files 1.5.2. Partial Reconfiguration Bitstream Compatibility Checking 1.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 1.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
1.6.1. Generating Programming Files for HPS Boot First Boot Flows 1.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
1.7. Scripting Support x
1.7.1. quartus_pfg Command Line Tool 1.7.2. quartus_cpf Command Line Tool
1.7.2. quartus_cpf Command Line Tool x
1.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
2. Using the Quartus® Prime Programmer x
2.1. Quartus® Prime Programmer 2.2. Programming and Configuration Modes 2.3. Basic Device Configuration Steps 2.4. Specifying the Programming Hardware Setup 2.5. Programming with Flash Loaders 2.6. Verifying the Programming File Source with Project Hash 2.7. Using PR Bitstream Security Verification ( Stratix® 10 Designs) 2.8. Stand-Alone Programmer and Tools 2.9. Programmer Settings Reference 2.10. Scripting Support 2.11. Using the Quartus® Prime Programmer Revision History
2.4. Specifying the Programming Hardware Setup x
2.4.1. JTAG Chain Debugger Tool 2.4.2. Editing the Details of an Unknown Device 2.4.3. Running JTAG Daemon with Linux
2.4.1. JTAG Chain Debugger Tool x
2.4.1.1. JTAG Chain Integrity Tab 2.4.1.2. JTAG Chain Debugging Tab
2.5. Programming with Flash Loaders x
2.5.1. Specifying Flash Partitions 2.5.2. Full Erase of Flash Memory Sectors
2.6. Verifying the Programming File Source with Project Hash x
2.6.1. Obtaining Project Hash for Arria® 10 Devices
2.8. Stand-Alone Programmer and Tools x
2.8.1. Stand-Alone Programmer Memory Consumption
2.9. Programmer Settings Reference x
2.9.1. Device & Pin Options Dialog Box 2.9.2. More Security Options Dialog Box 2.9.3. Output Files Tab Settings (Programming File Generator) 2.9.4. Input Files Tab Settings (Programming File Generator) 2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 2.9.6. Configuration Device Tab Settings 2.9.7. Add Partition Dialog Box (Programming File Generator) 2.9.8. Add Filesystem Dialog Box (Programming File Generator) 2.9.9. Convert Programming File Dialog Box 2.9.10. Compression and Encryption Settings (Convert Programming File) 2.9.11. SOF Data Properties Dialog Box (Convert Programming File) 2.9.12. Select Devices (Flash Loader) Dialog Box
2.10. Scripting Support x
2.10.1. The jtagconfig Debugging Tool
3. Using the HPS Flash Programmer x
3.1. Supported Devices 3.2. HPS Flash Programmer Command-Line Utility 3.3. How the HPS Flash Programmer Works 3.4. Using the Flash Programmer from the Command Line 3.5. Supported Memory Devices 3.6. HPS Flash Programmer User Guide Revision History
3.4. Using the Flash Programmer from the Command Line x
3.4.1. HPS Flash Programmer 3.4.2. HPS Flash Programmer Command Line Examples
Answers to Top FAQs
1. Quartus® Prime Programmer User Guide
2. Using the Quartus® Prime Programmer
3. Using the HPS Flash Programmer
A. Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Quartus® Prime Pro Edition User Guides

3.5. Supported Memory Devices

Table 43.  QSPI Flash
Flash Device Manufacturer Device ID DIE # Density (Mb) Voltage
M25P40 Micron 0x132020 1 4 3.3
N25Q064 Micron 0x17BA20 1 64 3.3
N25Q128 Micron 0x18BA20 1 128 3.3
N25Q128 Micron 0x18BB20 1 128 1.8
N25Q256 Micron 0x19BA20 1 256 3.3
N25Q256 Micron 0x19BB20 1 256 1.8
MT25QL512 Micron 0x20BA20 1 512 3.3
N25Q512 Micron 0x20BA20 2 512 3.3
MT25QU512 Micron 0x20BB20 1 512 1.8
N25Q512A Micron 0x20BB20 2 512 1.8
N25Q00AA Micron 0x21BA20 4 1024 3.3
MT25QU01G Micron 0x21BB20 2 1024 1.8
N25Q00AA Micron 0x21BB20 4 1024 1.8
MT25QL02G Micron 0x22BA20 4 2048 3.3
MT25QU02G Micron 0x22BB20 4 2048 1.8
S25FL128S Cypress 0x182001 1 128 (64KB Sectors) 3.3
S25FL128S Cypress 0x182001 1 128 (256KB Sectors) 3.3
S25FL256S Cypress 0x190201 1 256 (64KB Sectors) 3.3
S25FL256S Cypress 0x190201 1 256 (256KB Sectors) 3.3
S25FL512S Cypress 0x200201 1 512 3.3
MX25L12835E Macronix 0x1820C2 1 128 3.3
MX25L25635 Macronix 0x1920C2 1 256 3.3
MX66L51235F Macronix 0x1A20C2 1 512 3.3
MX66L1G45 Macronix 0x1B20C2 1 1024 3.3
MX66U51235 Macronix 0x3A25C2 1 512 1.8
GD25Q127C GigaDevice 0x1840C8 1 128 3.3
Table 44.  ONFI Compliant NAND Flash
Manufacturer MFC ID Device ID Density (Gb)

Micron

0x2C

0x68

32

Micron

0x2C

0x48

16

Micron

0x2C

0xA1

8

Micron

0x2C

0xF1

8

Note: The above table contains just examples of supported devices. The HPS Flash Programmer supports all ONFI compliant NAND flash devices that are supported by the HPS QSPI Flash Controller.
Note: The HPS Flash Programmer supports Arria® 10 devices. For more information, refer to the "Supported Flash Devices for Arria® 10" web page.
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