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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices
1.4. Enabling Bitstream Encryption or Compression for Arria® 10 and Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Stratix® 10 Designs)
2.8. Stand-Alone Programmer and Tools
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Add Filesystem Dialog Box (Programming File Generator)
2.9.9. Convert Programming File Dialog Box
2.9.10. Compression and Encryption Settings (Convert Programming File)
2.9.11. SOF Data Properties Dialog Box (Convert Programming File)
2.9.12. Select Devices (Flash Loader) Dialog Box
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1.2.2.3. Debugging the Configuration (Convert Programming Files)
Click the Advanced option in the Convert Programming Files dialog box to debug the file conversion configuration. Only choose advanced settings that apply to the design's target Intel FPGA device.
Changes in the Advanced Options dialog box affect .pof, .jic, .rpd, and .rbf file generation.
The following table describes the Advanced Options settings:
| Option Setting | Description | Values |
|---|---|---|
| Disable EPCS/EPCQ ID check | Directs the FPGA to skips the EPCS/EPCQ silicon ID verification. Applies to single and multi device AS configuration modes on all devices. |
Default setting is ON (EPCS/EPCQ ID check is enabled). |
| Disable AS mode CONF_DONE error check | Directs the FPGA to skip the CONF_DONE error check. Applies to single- and multi-device (AS) configuration modes on all devices. |
Default setting is OFF (AS mode CONF_DONE error check is enabled). |
| Program Length Count adjustment | Specifies the offset you can apply to the computed PLC of the entire bitstream. Applies to single- and multi-device (AS) configuration modes on all FPGA devices. |
Integer (Default = 0) |
| Post-chain bitstream pad bytes | Specifies the number of pad bytes appended to the end of an entire bitstream. | If the bitstream of the last device is uncompressed, default value is 0. Otherwise, default is 2 |
| Post-device bitstream pad bytes | Specifies the number of pad bytes appended to the end of the bitstream of a device. Applies to all single-device configuration modes on all FPGA devices. |
Zero or positive integer. Default is 0 |
| Bitslice Padding Value | Specifies the padding value used to prepare bitslice configuration bitstreams, such that all bitslice configuration chains simultaneously receive their final configuration data bit. Use only in 2, 4, and 8-bit PS configuration mode, when you use an EPC device with the decompression feature enabled. Applies to all FPGA devices that support enhanced configuration devices. |
0 or 1 Default value is 1 |
The following table lists possible symptoms of a failing configuration, and describes the advanced options necessary for configuration debugging.
| Failure Symptoms | Disable EPCS/EPCQ ID Check | Disable AS Mode CONF_DONE Error Check | PLC Settings | Post-Chain Bitstream Pad Bytes | Post-Device Bitstream Pad Bytes | Bitslice Padding Value |
|---|---|---|---|---|---|---|
| Configuration failure occurs after a configuration cycle. | — | Yes | Yes | Yes 1 | Yes 2 | — |
| Decompression feature is enabled. | — | Yes | Yes | Yes 1 | Yes 2 | — |
| Encryption feature is enabled. | — | Yes | Yes | Yes 1 | Yes 2 | — |
| CONF_DONE stays low after a configuration cycle. | — | Yes | Yes 3 | Yes 1 | Yes 2 | — |
| CONF_DONE goes high momentarily after a configuration cycle. | — | Yes | Yes 4 | — | — | — |
| FPGA does not enter user mode even though CONF_DONE goes high. | — | — | — | Yes 1 | Yes 2 | — |
| Configuration failure occurs at the beginning of a configuration cycle. | Yes | — | — | — | — | — |
| EPCS128 | Yes | — | — | — | — | — |
| Failure in .pof generation for EPC device using Quartus® Prime Convert Programming File Utility when the decompression feature is enabled. | — | — | — | — | — | Yes |
1 Use only for multi-device chain
2 Use only for single-device chain
3 Start with positive offset to the PLC settings
4 Start with negative offset to the PLC settings