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1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
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2.3. Simulating the Design Example
The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the P-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.
Figure 15. PIO Design Example Simulation Testbench
![](/content/dam/docs/us/en/683038/23-2-9-0-2/hhc1592415179599.png)
For more details on the testbench and the modules in it, refer to Testbench.
The following flow diagram shows the steps to simulate the design example:
Figure 16. Procedure
- Change to the testbench simulation directory, <project_directory>/pcie_ed_tb/pcie_ed_tb/sim/<EDA_vendor>/simulator.
- Run the simulation script for the simulator of your choice. Refer to the table below.
- Analyze the results.
Note: P-Tile does not support parallel PIPE simulations.
The simulation reports, "Simulation stopped due to successful completion" if no errors occur.