P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683038
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.26 22.3 8.3.0
  • Updated the instructions in the Running the Performance Design Example section to include the step for choosing the payload size for DMA operations.
  • Updated the Running the SR-IOV Design Example section to include sample enumeration results of running an SR-IOV design example with multiple PFs and VFs.

2022.06.20 22.2 8.1.0
  • Added support for Gen3 x8 and Gen4 x8 modes to the PIO design example.
  • Removed support for the Intel® Stratix® 10 DX ES1 FPGA Development Kit from the Generating the Design Example section.
2022.03.28 22.1 8.0.0
  • Added the section Overview to describe the simulation and hardware testing support for all the design examples.
  • Added instructions on how to run the Riviera* simulator to the Simulating the Design Example section.
  • Added the section Running the Performance Design Example.
  • Added a note to the Running the Design Example section stating that the refclk switch on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ FPGA Development Kit must be set to the OFF position to select the common refclk from the PCIe Edge Connector for PCIe link stability.
2021.12.15 21.4 7.0.0
  • Added the section Hardware and Software Requirements.
  • Added the description for the Performance design example to the Design Example Description section.
  • Added steps to generate the Performance design example to the Generating the Design Example section.
  • Added the description for the Performance design example testbench to the Simulating the Design Example section.
2021.10.04 21.3 6.0.0
  • Changed the supported configurations for the SR-IOV design example from Gen3 x16 EP and Gen4 x16 EP to Gen3 x8 EP and Gen4 x8 EP in the Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example section.
  • Added the support for the Intel® Stratix® 10 DX P-tile Production FPGA Development Kit to the Generating the Design Example section.
2021.07.01 21.2 5.0.0
  • Removed the simulation waveforms for the PIO and SR-IOV design examples from the section Simulating the Design Example.
  • Updated the command to display the BDF in the section Running the PIO Design Example.
2020.10.05 20.3 3.1.0 Removed the Registers section since the Avalon Streaming design examples have no control register.
2020.07.10 20.2 3.0.0
  • Added simulation waveforms, test case descriptions and test result descriptions for the design examples.
  • Added simulation instructions for the ModelSim simulator to the Simulating the Design Example section.
2020.05.07 20.1 2.0.0
  • Updated the document title to Intel FPGA P-Tile Avalon® streaming IP for PCI Express* Design Example User Guide to meet new legal naming guidelines.
  • Updated the VCS interactive mode simulation command.
2019.12.16 19.4 1.1.0 Added SR-IOV design example description.
2019.11.13 19.3 1.0.0 Added Gen4 x8 Endpoint and Gen3 x8 Endpoint to the list of supported configurations.
2019.05.03 19.1.1 1.0.0 Initial release.
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