Intel® Agilex™ Variable Precision DSP Blocks User Guide

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ID 683037
Date 11/17/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ Variable Precision DSP Blocks Overview 2. Intel® Agilex™ Variable Precision DSP Blocks Architecture 3. Intel® Agilex™ Variable Precision DSP Blocks Operational Modes 4. Intel® Agilex™ Variable Precision DSP Blocks Design Considerations 5. Native Fixed Point DSP Intel® Agilex™ FPGA IP Core References 6. Multiply Adder Intel® FPGA IP Core References 7. ALTMULT_COMPLEX Intel® FPGA IP Core Reference 8. LPM_MULT Intel® FPGA IP Core References 9. LPM_DIVIDE (Divider) Intel FPGA IP Core 10. Native Floating Point DSP Intel® Agilex™ FPGA IP References 11. Intel® Agilex™ Variable Precision DSP Blocks User Guide Archives 12. Document Revision History for the Intel® Agilex™ Variable Precision DSP Blocks User Guide
1. Intel® Agilex™ Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Intel® Agilex™ Devices
1.2. Supported Operational Modes in Intel® Agilex™ Devices x
1.2.1. Fixed-point Arithmetic 1.2.2. Floating-point Arithmetic
2. Intel® Agilex™ Variable Precision DSP Blocks Architecture x
2.1. Fixed-point Arithmetic 2.2. Floating-point Arithmetic
2.1. Fixed-point Arithmetic x
2.1.1. Input Register Bank for Fixed-point Arithmetic 2.1.2. Pipeline Registers for Fixed-point Arithmetic 2.1.3. Pre-adder for Fixed-point Arithmetic 2.1.4. Internal Coefficient for Fixed-point Arithmetic 2.1.5. Multipliers for Fixed-point Arithmetic 2.1.6. Adder or Subtractor for Fixed-point Arithmetic 2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic 2.1.8. Systolic Register for Fixed-point Arithmetic 2.1.9. Double Accumulation Register for Fixed-point Arithmetic 2.1.10. Output Register Bank for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic x
2.1.7.1. Dynamic Chainout
2.2. Floating-point Arithmetic x
2.2.1. Input Register Bank for Floating-point Arithmetic 2.2.2. Pipeline Registers for Floating-point Arithmetic 2.2.3. Multipliers for Floating-point Arithmetic 2.2.4. Adder or Subtractor for Floating-point Arithmetic 2.2.5. Output Register Bank for Floating-point Arithmetic 2.2.6. Exception Handling for Floating-point Arithmetic
3. Intel® Agilex™ Variable Precision DSP Blocks Operational Modes x
3.1. Operational Modes for Fixed-point Arithmetic 3.2. Operational Modes for Floating-point Arithmetic
3.1. Operational Modes for Fixed-point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 4 Mode 3.1.3. Multiplier Adder Sum Mode 3.1.4. Independent Complex Multiplier 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.4. Independent Complex Multiplier x
3.1.4.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode
3.1.5. Systolic FIR Mode x
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-point Arithmetic x
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions 3.2.2. FP16 Half-precision Floating-point Arithmetic Functions 3.2.3. Multiple Floating-point Variable DSP Blocks Functions
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions x
3.2.1.1. FP32 Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode 3.2.1.4. FP32 Vector One Mode 3.2.1.5. FP32 Vector Two Mode
3.2.2. FP16 Half-precision Floating-point Arithmetic Functions x
3.2.2.1. FP16 Supported Precision Formats 3.2.2.2. Sum of Two FP16 Multiplication Mode 3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode 3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode 3.2.2.5. FP16 Vector One Mode 3.2.2.6. FP16 Vector Two Mode 3.2.2.7. FP16 Vector Three Mode
3.2.3. Multiple Floating-point Variable DSP Blocks Functions x
3.2.3.1. Multiply-Add or Multiply-Subtract Mode 3.2.3.2. Direct Vector Dot Product 3.2.3.3. Complex Multiplication
4. Intel® Agilex™ Variable Precision DSP Blocks Design Considerations x
4.1. Fixed-point Arithmetic 4.2. Floating-point Arithmetic 4.3. DSP Block Cascade Limit in Intel® Agilex™ Devices
4.1. Fixed-point Arithmetic x
4.1.1. Configurations for Input, Pipeline, and Output Registers 4.1.2. Internal Coefficient and Pre-Adder for Fixed-point Arithmetic 4.1.3. Accumulator for Fixed-point Arithmetic 4.1.4. Input Cascade for Fixed-point Arithmetic 4.1.5. Chainout Adder
4.1.1. Configurations for Input, Pipeline, and Output Registers x
4.1.1.1. Restrictions for Input Registers 4.1.1.2. Restrictions for Pipeline Registers 4.1.1.3. Supported Register Configurations per Operation Modes
4.1.4. Input Cascade for Fixed-point Arithmetic x
4.1.4.1. Dynamic Scanin
4.2. Floating-point Arithmetic x
4.2.1. Configurations for Input, Pipeline, and Output Registers 4.2.2. Chainout Adder
4.2.1. Configurations for Input, Pipeline, and Output Registers x
4.2.1.1. FP32 Operation Modes Supported Register Configurations 4.2.1.2. FP16 Operation Mode Supported Register Configurations
5. Native Fixed Point DSP Intel® Agilex™ FPGA IP Core References x
5.1. Native Fixed Point DSP Intel® Agilex™ FPGA IP Release Information 5.2. Supported Operational Modes 5.3. Maximum Input Data Width for Fixed-point Arithmetic 5.4. Maximum Output Data Width for Fixed-point Arithmetic 5.5. Parameterizing Native Fixed Point DSP IP 5.6. Native Fixed Point DSP Intel® Agilex™ FPGA IP Signals
5.3. Maximum Input Data Width for Fixed-point Arithmetic x
5.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
5.5. Parameterizing Native Fixed Point DSP IP x
5.5.1. Operation Mode Tab 5.5.2. Input Cascade Tab 5.5.3. Pre-adder Tab 5.5.4. Internal Coefficient Tab 5.5.5. Accumulator/Output Chaining 5.5.6. Pipelining 5.5.7. Clear Signal
5.6. Native Fixed Point DSP Intel® Agilex™ FPGA IP Signals x
5.6.1. 9 × 9 Sum of 4 Mode Signals 5.6.2. 18 × 18 Full Mode Signals 5.6.3. 18 × 18 Sum of Two Mode Signals 5.6.4. 18 × 18 Plus 36 Mode Signals 5.6.5. 18 × 18 Systolic Mode Signals 5.6.6. 27 × 27 Mode Signals
6. Multiply Adder Intel® FPGA IP Core References x
6.1. Multiply Adder Intel® FPGA IP Release Information 6.2. Features 6.3. Parameters 6.4. Signals
6.2. Features x
6.2.1. Pre-adder 6.2.2. Systolic Delay Register 6.2.3. Pre-load Constant 6.2.4. Double Accumulator
6.2.1. Pre-adder x
6.2.1.1. Pre-adder Simple Mode 6.2.1.2. Pre-adder Coefficient Mode 6.2.1.3. Pre-adder Input Mode 6.2.1.4. Pre-adder Square Mode 6.2.1.5. Pre-adder Constant Mode
6.3. Parameters x
6.3.1. General Tab 6.3.2. Extra Modes 6.3.3. Multipliers Tab 6.3.4. Preadder Tab 6.3.5. Accumulator Tab 6.3.6. Systolic/Chainout Tab 6.3.7. Pipelining Tab
7. ALTMULT_COMPLEX Intel® FPGA IP Core Reference x
7.1. ALTMULT_COMPLEX Intel® FPGA IP Release Information 7.2. Features 7.3. Complex Multiplication 7.4. Parameters 7.5. Signals
8. LPM_MULT Intel® FPGA IP Core References x
8.1. LPM_MULT Intel® FPGA IP Release Information 8.2. Features 8.3. Parameters 8.4. Signals
8.3. Parameters x
8.3.1. General Tab 8.3.2. General 2 Tab 8.3.3. Pipelining Tab
9. LPM_DIVIDE (Divider) Intel FPGA IP Core x
9.1. LPM_DIVIDE Intel® FPGA IP Release Information 9.2. Features 9.3. Verilog HDL Prototype 9.4. VHDL Component Declaration 9.5. VHDL LIBRARY_USE Declaration 9.6. Ports 9.7. Parameters
9.7. Parameters x
9.7.1. General Tab 9.7.2. General1 Tab
10. Native Floating Point DSP Intel® Agilex™ FPGA IP References x
10.1. Native Floating Point DSP Intel® Agilex™ FPGA IP Release Information 10.2. Native Floating Point DSP Intel® Agilex™ FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Intel® Agilex™ FPGA IP 10.4. Native Floating Point DSP Intel® Agilex™ FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Intel® Agilex™ FPGA IP x
10.3.1. General Tab 10.3.2. Registers Tab
10.4. Native Floating Point DSP Intel® Agilex™ FPGA IP Core Signals x
10.4.1. FP32 Multiplication Mode Signals 10.4.2. FP32 Addition or Subtraction Mode Signals 10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals 10.4.4. FP32 Multiplication with Accumulation Mode Signals 10.4.5. FP32 Vector One and Vector Two Modes Signals 10.4.6. Sum of Two FP16 Multiplication Mode Signals 10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals 10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals 10.4.9. FP16 Vector One and Vector Two Modes Signals 10.4.10. FP16 Vector Three Mode Signals
1. Intel® Agilex™ Variable Precision DSP Blocks Overview
2. Intel® Agilex™ Variable Precision DSP Blocks Architecture
3. Intel® Agilex™ Variable Precision DSP Blocks Operational Modes
4. Intel® Agilex™ Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Intel® Agilex™ FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core Reference
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE (Divider) Intel FPGA IP Core
10. Native Floating Point DSP Intel® Agilex™ FPGA IP References
11. Intel® Agilex™ Variable Precision DSP Blocks User Guide Archives
12. Document Revision History for the Intel® Agilex™ Variable Precision DSP Blocks User Guide

8.4. Signals

Table 101.   LPM_MULT Intel® FPGA IP Core Input Signals
Signal Name Required Description
dataa[] Yes Data input.

The size of the input signal depends on the Dataa width parameter value.

datab[] Yes Data input.

The size of the input signal depends on the Datab width parameter value.

clock No Clock input for pipelined usage.

For Latency values other than 1 (default), the clock signal must be enabled.

clken No Clock enable for pipelined usage. When the clken signal is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear signal used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
sclr No Synchronous clear signal used at any time to reset the pipeline to all 0s, synchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
Table 102.   LPM_MULT Intel® FPGA IP Output signals
signal Name Required Description
result[] Yes Data output.

The size of the output signals depends on the Result width parameter.

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