50G Interlaken Design Example User Guide

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ID 683029
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 50G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 50G Interlaken Design Example User Guide

2.6. Register Map

Table 3.  Example Design Register Map
Offset Name Access Description
8'h00 Reserved
8'h01 Reserved
8'h02 System PLL reset RO Following bits indicates system PLL reset request and enable value:
  • Bit [0] - sys_pll_rst_req
  • Bit [1] - sys_pll_rst_en
8'h03 RX lane aligned RO Indicates the RX lane alignment.
8'h04 WORD locked RO [NUM_LANES–1:0] – Word (block) boundaries identification.
8'h05 Sync locked RO [NUM_LANES–1:0] – Metaframe synchronization.
8'h06 - 8'h09 CRC32 error count RO Indicates the CRC32 error count.
8'h0A CRC24 error count RO Indicates the CRC24 error count.
8'h0B Overflow/Underflow signal RO Following bits indicate:
  • Bit [3] - TX underflow signal
  • Bit [2] - TX overflow signal
  • Bit [1] - RX overflow signal
8'h0C SOP count RO Indicates the number of SOP.
8'h0D EOP count RO Indicates the number of EOP
8'h0E Error count RO Indicates the number of following errors:
  • Loss of lane alignment
  • Illegal control word
  • Illegal framing pattern
  • Missing SOP or EOP indicator
8'h0F send_data_mm_clk RW Write 1 to enable the generator signal.
8'h10 Reserved
8'h11 System PLL lock RO PLL lock indication.
Note:
  • Example design register address starts with 0x20** while the 50G Interlaken core register address starts with 0x10**.
  • Access code: RO—Read Only, and RW—Read/Write.
  • System console reads the example design registers and reports the test status on the screen.
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