50G Interlaken Design Example User Guide

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ID 683029
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 50G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 50G Interlaken Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 19.2.0
The Intel® Arria® 10 variations of the 50G Interlaken IP core feature a simulating testbench and a hardware example design that supports compilation and hardware testing, to help you understand usage.

When you generate the example design, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to the Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit. The testbench and demonstration example design are available for a wide range of parameters. However, they do not cover all possible parameterizations of the 50G Interlaken IP Core.

In addition, for most IP core variations, Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Development Steps
Level Two Title