F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

Document Version Quartus® Prime Version Changes
2024.11.20 24.3 Made the following changes:
  • Updated step 4 about calculating occupancy values for PTP in the RX Virtual Lane Offset Calculation for No FEC Variants.
  • Corrected [7:0] to SFD and [63:56] to the Start of Packet control byte in the figure Byte Order on the Avalon Streaming Interface Lanes With Preamble Pass-Through in the Order of Ethernet Transmission.
  • Corrected the latency from o_tx_mac_ready to i_tx_mac_valid is 1-7 clock cycles in TX Max Segmented Client Interface.
  • Corrected i_tx_mac_data to o_rx_mac_data and i_tx_mac_inframe to o_rx_mac_inframe in RX MAC Segmented Client Interface.
  • Added the following tables in PCS Mode TX Interface.
    • Alignment Marker Insertion Periods
    • Alignment Marker Insertion Periods for Simulation with Non-PTP Enabled Modes
    • Alignment Marker Insertion Periods for Simulation with PTP Enabled modes
  • Updated step 2 in PTP RX Client Flow.
  • Added port_state signal to the AN/LT IP when DR is selected in the Base IP port connections table of the Clocks and Resets section.
2024.07.08 24.2 Made the following changes:
  • Removed the following conflicting and confusing statement from TX MAC Segmented Client Interface.
    • The i_tx_mac_valid may go low during the packet transmission.
  • Updated the i_tx_mac_valid signal deasserts when the o_tx_mac_ready signal is deasserted in TX MAC Segmented Client Interface.
  • Replaced word address with Byte address for the port name i_reconfig_ptp_asym_addr[16:0] in PTP Asymmetry Delay Reconfiguration Interface.
  • Updated i_stats_snapshot signal description in the Status Signals table of Status Interface topic.
2024.06.05 24.1 Added a note that states: When a link fault occurs in the receive direction, the IP clears the RX statistic counters in Datapath Description under the Functional Description section.
2024.04.01 24.1 Made the following changes:
  • Added Agilex™ 9 device family support.
  • Updated FlexE and OTN Mode Interface topic.
  • Corrected o_tx_pll_lanes_stable to o_tx_lanes_stable in PCS Mode TX Interface.
2024.03.11 23.4 Updated the following images in Clock Connections in Synchronous Ethernet Operation.
  • Enable Dedicated CDR Clock Output IP Parameter Editor.
  • Select Designs Example Design.
2023.12.04 23.4 Made the following changes:
  • Updated resource utilization table due to changes from Nios II to Nios V.
  • Corrected the description for Stop TX traffic when link partner sends PAUSE parameter in Parameters.
  • Added new IP Parameter: Enable IPXACT in Parameters.
  • Updated TX and RX table fields for UI Value and PMA Delay of Ethernet Modes in UI Value and PMA Delay.
  • Removed the restrictions on PTP support for Agilex 7 041 devices in Device Speed Grade Support.
203.10.02 23.3 Made the following changes:
  • Corrected the i_ptp_ts_offset description and image in TX 1-Step Timestamp Interface.
  • Added F-Tile Ethernet Intel® FPGA Hard IP Parameters: IP Tab screenshot with Analog parameters tab in F-Tile Ethernet Intel® FPGA Hard IP Parameters.
  • Removed the IP Parameter: Include Deterministic Latency Interface in Parameter section.
  • Removed Deterministic latency Interface topic in Interface Overview section.
  • Added F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP parameter screenshot with Target Profile Settings tab.
  • Added the following parameters in the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters section:
    • Enable AN/LT Debug Endpoint for Ethernet Toolkit
    • Enable Fast Simulation
    • Enable Dynamic AN/LT
2023.06.26 23.2
  • Updated alignment marker verbiage in OTN Mode.
  • Added note in PTP RX Client Flow.
  • Added description about alignment marker for the signal name i_tx_pcs66_am inSignals of the PCS66 TX Interface table.
  • Updated ANLT functional description in Supported Modules and IPs.
  • Added note under AN channel in AN/LT parameters IP tab.
  • Added a verbiage about converting byte addresses to word addresses by shifting 2 bits to the right (divide by 4) in Registers.
  • Added a note verbiage "unauthorized access to register sets outside of the configured Ethernet fractures is not recommended" in Configuration Registers.
2023.04.03 23.1
  • Updated the following in the Round-trip latency table.
    • All the IEEE 802.3 RS(544,514) replaced with IEEE 802.3 RS(528,514) (CL91).
    • All the IEEE 802.3 RS(528,514) (CL91) replaced with IEEE 802.3 RS(544,514) (CL134).
  • Added steps to retrieve the N divider value in Clock Connections in Synchronous Ethernet Operation.
  • Removed the note "Enable TX packing feature is not available when PTP is turned on" in TX Packing Logic.
  • Updated ALMs numbers in TX Packing Logic section.
  • Updated Features in Precision Time Protocol section to include 200GE and 400GE modes for timestamp accuracy in advance mode.
  • Updated 200GE and 400GE Ethernet Data Rate to ± 1.5ns for advanced accuracy mode in PTP Timestamp Accuracy.
  • Added new topic: Routing Delay Adjustment for Basic Timestamp Accuracy Mode.
  • Updated the product family name to "Intel Agilex 7."
2022.12.19 22.4 Made the following changes:
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to remove filler text in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added the following footnotes in Variant Selection table.
    • The Auto-negotiation and link training hardware is available for no FEC, IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91).
    • The Auto-negotiation and link training is not available for IEEE 802.3 RS(544,514) (CL134).
  • Updated note about core speed grades for IP core variation with PTP in Device Speed Grade Support.
  • Added note about only 10GE with PTP support in advanced mode for OPNs AGIB041R29D1E2VR0, AGID041R29D1E2VR0, or any device density code of 041 in Device Speed Grade Support.
  • Added new topic: Round-trip Latency in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added the following parameters:
    • Include Deterministic Latency Measurement
    • Advanced Mode
    • Custom Ethernet line rate
  • Updated Include 32-bit soft CWBIN Counters default setting to Off in Parameters.
  • Updated Enable TX packing Parameter Description in Parameters.
  • Added i_sampling_clk in Clocks.
  • Added content for Example Design Generation of Synchronous Ethernet Operation in Clock Connections in Synchronous Ethernet Operation.
  • Updated the code for calculate pulse adjustment and FEC variants in PTP RX Client Flow.
  • Added a description for i_tx_pcs66_am in FlexE and OTN Mode TX Interface.
  • Added a description for o_rx_pcs66_am_valid in FlexE and OTN Mode RX Interface.
  • Added new subsection Deterministic Latency Measurement
  • Added auto-negotiation and link training feature note in Reset Signals.
  • Added reference to Pipelined Transfers of Avalon Interface Specifications in Reconfiguration Interfaces.
2022.09.26 22.3 Made the following changes:
  • Added Core Speed Grade/Transceiver Speed Grade table in Device Speed Grade Support.
  • Updated IP-XACT file information in Generating IP-XACT File.
  • Updated F-Tile Ethernet Intel FPGA Hard IP Block Diagram to include CWBIN in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Added 32-bit soft CWBIN counters parameter description in F-Tile Ethernet Intel FPGA Hard IP Overview.
  • Updated Release Information.
  • Added Include 32bit soft CWBIN counters and Reconfig clock frequency parameters in F-Tile Ethernet Intel FPGA Hard IP Parameters.
  • Added Enable IEEE 1588 PTP parameter description "When disabled, connect this port to 1'b0" in Clock Signals table.
  • Added new topic: 32-bit Soft CWBIN Counters.
  • Added note about auto-negotiation and link training bonding support for B0 FHT multi-lane designs in AN/LT Functional Description.
  • Added new topic: Implementation of Synchronous Ethernet (syncE) operation in Clocks section.
  • Corrected o_rx_mac_status_data's value 3'd3 to reserved in RX MAC Segmented Client Interface section.
2022.06.20 22.2 Made the following changes:
  • Updated note in Device Speed Grade Support.
  • Updated the PCS Mode RX Interface section to fix Hardware AM Cycle numbers.
  • Updated the Client Flow Glossary table in PTP Client Flow section. Added a row FL-Total number of FEC lanes of the variant.
  • Added new topic: Deterministic latency Interface
  • Added new topic: TX Packing Logic.
  • Added Enable TX Packing and Include Deterministic Latency Interface parameters in F-Tile Ethernet Intel® FPGA Hard IP Parameters.
  • Fixed the broken link F-Tile Channel Placement Tool in Supported Tools.
2022.03.28 22.1 Made the following changes:
  • Updated the Variant Selection table. The Auto-negotiation and link training hardware is available for FHT NRZ 25GE-1, 50GE-2, and 100GE-4.
  • Added transceiver speed grade-related information in Device Speed Grade Support.
  • Added IP-XACT statement in Specifying the IP Core Parameters and Options.
  • Added new topic: Generating IP-XACT File
  • Updated caution note in Frame Padding to clarify 9-byte payload requirements.
  • Re-ordered step 7 and step 8 in PTP TX Client Flow.
  • Re-ordered step 9 and step 10 in PTP RX Client Flow.
  • Updated TX/RX hardware PMA delay for FHT transceivers in the UI Value and PMA Delay of Ethernet Modes table.
  • Updated the Clocks section to remove the PTP clock limitation. The PTP clock runs at 100 to 250 MHz.
  • Removed the CRC bytes statement in RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding.
  • Added reference to the .ipxact file generation in Configuration Registers.
  • Revised the i_rst_n reset description in the PTP Tile Adapter: Clocks, Reset, and Interface Ports section.
  • Removed Verilog file format specific note from the Auto-Negotiation and Link Training Parameters section. The IP supports VHDL for synthesis and simulation.
  • Updated F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives.
2022.01.07 21.4 Made the following changes:
  • Updated F-Tile Ethernet Intel® FPGA Hard IP :
    • Added note about auto-negotiation and link training hardware support in Overview.
    • Added new section: Device Speed Grade Support.
    • Updated Generating Tile Files to include quartus_tlg updates.
    • Added the FHT precoding enable and Enable Native PHY Debug Endpoint parameters in the F-Tile Ethernet Intel® FPGA Hard IP Parameters.
    • Added PTP-specific i_reconfig_clk frequency range limitation.
  • Updated F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP :
    • Removed outdated 21.3 specific statement in Overview.
    • Updated Release Information.
    • Added note about VHDL limitation in F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP Parameters.
2021.10.04 21.3 Made the following changes:
  • Added support for PCS lane re-ordering in the Features table.
  • Removed 400GE-8 specific footnote from the Variant Selection table. 400GE-4 mode now supports auto-negotiation and link training.
  • Revised PTP description in F-Tile Ethernet Intel® FPGA Hard IP Overview,
  • Added Resource Utilization.
  • Updated F-Tile Ethernet Intel® FPGA Hard IP Parameters: IP Tab table:
    • Updated PMA reference frequency description.
    • Added PTP-related frequency requirements in the System PLL frequency description.
    • Added important note about hardware accuracy values in the Timestamp accuracy mode description.
    • Added new Enable Ethernet Debug Master Endpoint parameter
  • Added note in the TX MAC Segmented Client Interface.
  • Updated the TX TAM adjust calculation in PTP TX Client Flow.
  • Updated the RX TAM adjust calculation in PTP RX Client Flow.
  • Added new section: Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
  • Updated Precision Time Protocol Interface:
    • Removed 40G Ethernet rate from the PTP Clocks table. 40G Ethernet rate does not support PTP feature
    • Corrected i_clk_tx_tod clock frequency from 250 MHz to 114.2857 MHz..
  • Revised step 6 in RX UI Adjustment.
  • Update simulation-based RX TAM values for 50G Ethernet rate in Reference Time (TAM) Interval.
  • Updated Hardware UX PMA delay values in the UI Value and PMA Delay of Ethernet Modes table.
  • Globally added a note about PTP timestamp accuracy. The note emphasizes that the specified timestamp accuracy values in base and advanced modes represent simulation-based results.
  • Updated Clock Signals descriptions for the following clock signals:
    • i_clk_tx
    • i_clk_rx
    • i_clk_pll
    • i_clk_ref
  • Revised text and updated figure in Clock Connections in PTP-Based Synchronous and Asynchronous Operation.
  • Corrected signal name from i_sl_tx_valid to i_tx_valid in the TX MAC Avalon ST Client Interface.
  • Revised fixed latency range in TX MAC Segmented Client Interface. The i_tx_mac_valid and o_tx_mac_ready signals can be spaced by a fixed latency between 1 to 8 clock cycles.
  • Revised i_clk_ptp_sample clock description in the PTP Clock Ports table.
  • Added new topic: Ethernet Toolkit Overview
2021.06.28 21.2 Initial release
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