F-Tile Ethernet Intel® FPGA Hard IP User Guide

Download PDF
ID 683023
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

7.8. PCS Mode RX Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Table 51.  Signals of the MII RX Client InterfaceAll interface signals are clocked by the RX clock. The signal names are standard Avalon® streaming interface signals.

Signal Name

Width

Description

o_rx_mii_d[1023:0]

o_rx_mii_d[511:0]

o_rx_mii_d[255:0]

o_rx_mii_d[127:0]

o_rx_mii_d[63:0]

1024 bits (400GE)

512 bits (200GE)

256 bits (100GE)

128 bits (40GE/50GE)

64 bits(10GE/25GE)

RX MII data. Data is in MII encoding. o_rx_mii_d[7:0] holds the first byte the IP core received on the Ethernet link. o_rx_mii_d[0] holds the first bit the IP core received on the Ethernet link.

When RX MII valid signal has the value of 0 or the RX valid alignment marker signal has the value of 1, the value on this signal is invalid.

o_rx_mii_c[127:0]

o_rx_mii_c[63:0]

o_rx_mii_c[31:0]

o_rx_mii_c[15:0]

o_rx_mii_c[7:0]

128 bits (400GE)

64 bits (200GE)

32 bits (100GE)

16 bits (40GE/50GE)

8 bits(10GE/40GE)

 RX MII control bits. Each bit corresponds to a byte of RX MII data. o_rx_mii_c[0] corresponds to o_rx_mii_d[7:0], o_rx_mii_c[1] corresponds to o_rx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

o_rx_mii_valid

1 bit Indicates that the RX MII data, RX MII control bits, and the RX valid alignment marker signals are valid.

o_rx_mii_am_valid

1 bit Indicates the IP core received a valid alignment marker on the Ethernet link.

When the RX MII valid signal has the value of 0, the value on this signal is invalid. The value of the RX MII valid signal may fall while the IP core is asserting this signal.

Figure 46. Receiving Data Using the PCS Mode RX Interface

The figure above shows how to read packets from the RX PCS using the PCS mode RX interface.

  • The packets are MII encoded.
    • Each byte in o_rx_mii_d has a corresponding bit in o_rx_mii_c that indicates whether the byte is a control byte or a data byte; for example, o_rx_mii_c[2] is the control bit for o_rx_mii_d[23:16].
  • The data is only valid when o_rx_mii_valid is high. The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low.
  • The byte order for the PCS mode RX interface is opposite of the byte order for the MAC segmented client interface. Bytes flow from LSB to MSB; the first byte that the core receives is o_rx_mii_d[7:0].
  • The bit order for the PCS mode RX interface is the same as the bit order of the MAC segmented client interface. The first bit that the core receives is o_rx_mii_d[0].
Note: The PCS mode RX interface is not SOP aligned. New packets can begin on any byte position that is divisible by 8 (PCS data is transferred in 8-byte blocks).
Table 52.  Reading a Start Packet Block with Preamble from a PCS Mode TX Interface
MII Data MII Control Ethernet Packet Byte
o_rx_mii_d[7:0] 0xFB o_rx_mii_c[0] 1 Start of Packet
o_rx_mii_d[15:8] 0x55 o_rx_mii_c[1] 0 Preamble
o_rx_mii_d[23:16] 0x55 o_rx_mii_c[2] 0 Preamble
o_rx_mii_d[31:24] 0x55 o_rx_mii_c[3] 0 Preamble
o_rx_mii_d[39:32] 0x55 o_rx_mii_c[4] 0 Preamble
o_rx_mii_d[47:40] 0x55 o_rx_mii_c[5] 0 Preamble
o_rx_mii_d[55:48] 0x55 o_rx_mii_c[6] 0 Preamble
o_rx_mii_d[63:56] 0xD5 o_rx_mii_c[7] 0 SFD
Figure 47. Receiving Alignment Markers

o_rx_mii_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_mii_valid. When o_rx_mii_valid is low, o_rx_mii_am_valid is not valid.

The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low. This is because alignment markers are not part of the 64b/66b encoding, and do not have an MII equivalent.

Level Two Title