F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Round-trip Latency 1.2.5. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode 4.4.11. Routing Delay Adjustment for Basic Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. 32-bit Soft CWBIN Counters 7.13. Reconfiguration Interfaces 7.14. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.13. Reconfiguration Interfaces x
7.13.1. Ethernet Reconfiguration Interfaces 7.13.2. Transceiver Reconfiguration Interfaces
7.14. Precision Time Protocol Interface x
7.14.1. Time-of-Day Interface 7.14.2. TX 2-Step Timestamp Interface 7.14.3. TX 1-Step Timestamp Interface 7.14.4. RX Timestamp Interface 7.14.5. PTP Status Interface 7.14.6. PTP Tile Interface
7.14.3. TX 1-Step Timestamp Interface x
7.14.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for the F-Tile Ethernet Intel® FPGA Hard IP User Guide

3. F-Tile Ethernet Intel® FPGA Hard IP Parameters

The F-Tile Ethernet Intel® FPGA Hard IP parameter editor provides the parameters you can set to configure your F-Tile Ethernet Intel® FPGA Hard IP variation and simulation and hardware design examples.

The F-Tile Ethernet Intel® FPGA Hard IP parameter has an IP tab, Example Design tab, and Analog Parameters tab.
Figure 5.  F-Tile Ethernet Intel® FPGA Hard IP Parameters: IP Tab

For information about the Example Design tab and Analog Parameters tab, refer to the F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide and Analog Parameters Options in F-Tile Architecture and PMA and FEC Direct PHY Intel FPGA IP User Guide.

Table 12.   F-Tile Ethernet Intel® FPGA Hard IP Parameters: IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.

Parameter

Range

Default Setting

Parameter Description

General Options
Advanced mode
  • On
  • Off
 Off
When turned on, enables the Custom Ethernet line rate option and allows you to access the following FEC modes for 25GE-1.
  • Fibre Channel RS(528,514)
  • Ethernet Technology Consortium RS(528, 514)
PMA type
  • FHT
  • FGT
 FGT

PMA Channel Type.

Selects the F-Tile based targeted PMA type. Each PMA has a different data rate range and compliance specifications.
  • FHT:
    • 24-29 Gbps NRZ
    • 48-58 Gbps NRZ and PAM4
    • 96-116 Gbps PAM4
  • FGT:
    • 1-32 Gbps NRZ
    • 20-58.125 PAM4 9
FHT precoding enable
  • Disabled
  • Enabled
 Disabled Enables the FHT precoding. Available for PAM4 modes, always disabled for NRZ modes.
Note: This feature is used during the auto-negotiatiation and link training. When link training is disabled, the FHT precoding is enabled.
Ethernet mode
  • 10GE-1
  • 25GE-1
  • 40GE-4
  • 50GE-2
  • 50GE-1
  • 100GE-4
  • 100GE-2
  • 100GE-1
  • 200GE-8
  • 200GE-4
  • 200GE-2
  • 400GE-8
  • 400GE-4
 10GE-1

Ethernet Configuration.

Specifies the overall port bandwidth across the number of physical lanes used by the port.

Term XGE-Y represents:
  • X is the overall bandwidth of the port
  • Y is the number of physical lanes used by port
Custom Ethernet line rate Varies based on the selected Ethernet mode. 25.78125 Gbps

When turned on, this option allows you to choose the custom Ethernet line rate up to the maximum ethernet rate supported.

This parameter is available when Advanced mode is enabled in the IP parameter editor.

Client interface
  • MAC segmented
  • MAC Avalon ST
  • MII PCS only
  • PCS66 OTN
  • PCS66 FlexE
 MAC segmented Selects data interface exposed to a client. Selected interface determines the Ethernet functional blocks enabled in the design.
  • MAC Avalon® ST supports up to 100GE Ethernet rates.
  • MAC segmented interface supports all Ethernet rates.
FEC mode
  • None
  • IEEE 802.3 BASE-R Firecode (CL74)10
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium RS(272, 258)
 None

Selects the FEC mode for each port.

The IP core supports the following FEC types
  • IEEE 802.3 BASE-R Firecode is available only for 25GE MAC modes.
  • IEEE 802.3 RS(528,514) is typically used for NRZ modes.
  • IEEE 802.3 RS(544,514) is typically used for PAM4 modes.
  • Ethernet Technology Consortium RS(272,258) is a low-latency substitute for RS(544,514).

For more information about FEC modes and the supported protocols, refer to the F-Tile Supported FEC Modes and Compliance Specifications table in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

PMA reference frequency
  • 156.250000
  • 312.500000
  • 322.265625
 156.250000 Selects the reference clock frequency used by the transceiver.

156.25 MHz is the recommended frequency for all Ethernet modes. This is the only supported frequency when using FHT or when auto-negotiation and link training (AN/LT) is enabled.

312.5 MHz is also supported when using FGT without AN/LT.

322.265625 MHz is supported when you select IEEE 802.3 BASE-R Firecode or RS(528,514), while using FGT without AN/LT.
System PLL frequency
  • 830.078125
  • 805.664062 11
  • 322.265625
  • Custom
 805.664062

Selects the System PLL frequency. The core clock is equivalent to this frequency divided by 2.

Recommended frequency based on selected FEC mode:
  • Use 830.078125 MHz or higher when you select IEEE 802.3 RS(544,514) (CL134) or Ethernet Technology Consortium RS(272, 258)
  • Use 805.6640625 MHz or higher when you select IEEE 802.3 RS(528,514) (CL91), IEEE 802.3 BASE-R Firecode (CL74), or no FEC. Also, use this frequency or higher when PTP is enabled, including the 10GE PTP option.
  • Use 322.265625 MHz or higher when you select 10GE without PTP.
  • Use Custom when you require other frequencies or if system PLL reference clock source and PMA reference clock source are different. You must define Custom System PLL Frequency parameter value.
    • When you select Custom, the IP internally includes a custom cadence controller.
    • When you require an external custom cadence controller, enable External Custom Cadence Controller parameter.
Custom system PLL Frequency

805.6640625 - 903.125 MHz

(with enabled PTP )

322.265625 - 1GHz

(with disabled PTP)

 N/A

If you choose the Custom option in the System PLL Frequency parameter, the IP core clock o_clk_pll is equivalent to half of the specified rate.

External Custom Cadence Controller
  • On
  • Off
 Off

When turned on, enables the external custom cadence controller option and allows you to drive the i_custom_cadence port to DUT. You can use the parameter when sharing custom cadence controller with multiple IP instances.

This parameter is available if you choose the Custom option in the System PLL Frequency parameter.

Include Deterministic Latency Measurement
  • On
  • Off
 Off

When turned on, enables the built-in Deterministic Latency Measurement module within the IP.

This parameter is available if you choose the PCS66 FlexE option in the Client interface parameter.
Note: This parameter and Include Deterministic Latency Interface cannot be enabled at the same time.
Include 32-bit soft CWBIN counters
  • On
  • Off
 Off This parameter is available when FEC mode is enabled in the IP parameter editor. This soft logic converts the 8-bit CWBin0-3 registers in Hard IP (FEC block of F-Tile) to the 32-bit registers in Soft logic.
Reconfig Clock Frequency 100 to 250 MHz 100 MHz Avalon® memory-mapped interface reconfiguration clock. The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency.
Enable dedicated CDR Clock Output
  • On
  • Off
 Off When turned on, enables the dedicated CDR clock output. When there is more than one channel number, the CDR clock output is connected to channel 0. This option is only applicable if the channel 0 is placed within FGT QUAD3 or UX FGT Quad2.

MAC Options

Basic Tab

TX maximum frame size

65 – 65535

1518

Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters.

In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518.

RX maximum frame size

65 – 65535

1518

Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters. If you turn on Enforce Maximum Frame Size parameter, the IP core truncates incoming Ethernet packets that exceed this size.

In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518.
Enforce maximum frame size
  • On
  • Off
 Off Specifies whether the IP core is able to receive an oversized packet or truncates these packets.

In a truncated packet, error signal indicates oversize and FCS error.

Link fault generation option
  • Off
  • Unidirectional
  • Bidirectional
 Off

Specifies the IP core response to link fault events.

Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.

Bytes to remove from RX frames
  • None
  • Remove CRC bytes
  • Remove CRC and PAD bytes
 Remove CRC bytes Selects whether the RX MAC should remove CRC bytes, or remove CRC and PAD bytes, or do not remove anything from incoming RX frames before passing them to the RX MAC Client. If the PAD bytes and CRC are not needed downstream, this option can reduce the need for downstream packet processing logic
Forward RX pause requests
  • On
  • Off
 O0ff Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface, or drops them after internal processing.
Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
Use source address insertion - -
When enabled, the IP inserts source address in outgoing packets.
Note: Use Hexadecimal values to insert source address.

Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface, but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of i_tx_pause or i_tx_pfc[n] on the TX MAC client interface.

TX VLAN detection
  • On
  • Off
 Off Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the TxFrameOctetsOK counter. If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
RX VLAN detection
  • On
  • Off
 Off Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frames in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the RxFrameOctetsOK counter . If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
Stop TX traffic when link partner sends PAUSE
  • No
  • Yes
  • Disable flow control
 No When set to Yes, both SFC and PFC are supported. When a pause frame is received, the TX MAC stops sending traffic. When set to No, both SFC and PFC are supported. When a pause frame is received, the TX MAC does not stop sending traffic. When set to Disable, flow control is disabled entirely.
Ready latency 0 - 3 0 Selects the ready Latency value on the TX client interface. readyLatency is an Avalon® ST interface property that defines the number of clock cycles of delay from when the IP core asserts the o_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications.

In MII PCS Only and MAC segmented variations, this parameter has no effect.

Selecting a longer latency (higher number) eases timing closure at the expense of increased latency for the TX datapath in MAC+PCS variations.

Enable TX Packing
  • On
  • Off
 Off

This parameter is available when Client interface is set to MAC segmented mode without PTP enabled for all rates ranging from 40G to 400G and with PTP enabled for all rates ranging from 50GE to 400GE

When set to On, packing logic is inserted in TX direction. It removes idle segments in between the packets and maximizes throughput of the MAC.

Enable asynchronous adapter clocks
  • On
  • Off
 Off When turned on, you may drive the i_clk_rx and i_clk_tx clock signals different from o_clk_pll clock.

Available only when Client interface is set to MAC Avalon® ST.

PTP Tab

Enable IEEE 1588 PTP
  • On
  • Off
 Off

Enable this option to add IEEE 1588 PTP Timestamp offload functions to the IP core. The IP core can generate TX timestamps and RX timestamps.

Timestamp accuracy mode
  • Basic
  • Advanced
 Advanced Select PTP TX and RX timestamps accuracy mode. 12
In Basic mode, supports the following timestamps accuracy:
  • ± 3ns for 10GE, and 25GE Ethernet rate
  • ± 8ns for 50GE, 100GE, 200GE, and 400GE Ethernet rate
In Advanced mode, supports the following timestamps accuracy:
  • ± 1.5ns for 10GE, 25GE, 50GE, 100GE, 200GE, and 400GE Ethernet rate
Timestamp fingerprint width 8 - 32 8

Specify the width of the timestamp fingerprint in bits on the TX path. The default value is 8 bits.

Specialized Tab

Enable strict preamble check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Enable strict SFD check
  • On
  • Off
 Off If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5).

This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.

Average inter-packet gap
  • 1
  • 8
  • 10
  • 12
 12

Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link. Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link.

The default value of 12 complies with the Ethernet standard.

The remaining values support increased throughput.

The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard but the application has control over the average gap and maximizing the throughput.

Enable preamble passthrough
  • On
  • Off
 Off

If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.

Additional IPG removed per AM period 0-16536 0

Specifies the number of inter-packet gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance.

Each increment of 1 in the value of Additional IPG removed per AM period increases throughput by 3ppm in 100GE variations. To specify larger throughput increases, use the Average Inter-packet Gap parameter.

Auto-Negotiation and Link Training Options
Enable auto-negotiation and link training
  • On
  • Off
 Off Enables auto-negotiation and link training for the Ethernet port.

You must instantiate the F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP to support this feature.

Configuration, Debug and Extension Options
Enable Ethernet Debug Endpoint
  • On
  • Off
 Off Enables the Ethernet debug endpoint.

You must enable this parameter to allow the System Console access the Ethernet toolkit.
Enable Native PHY Debug Endpoint
  • On
  • Off
 Off Enables the Native PHY debug endpoint.

You must enable this parameter to allow the System Console access the Transceiver toolkit.
Related Information
9 FGT Quad0 can only support 20-32 Gbps PAM4. FGT Quad1, Quad2, and Quad3 can support 20-58 Gbps PAM4.
10 This mode is only available for 25G Ethernet mode.
11 The IP GUI specifies the 805.664062 MHz frequency. The actual frequency is 805.6640625 MHz.
12 Ethernet modes without specified lane apply to all lane variants.
Level Two Title