Visible to Intel only — GUID: orb1600968305933
Ixiasoft
Visible to Intel only — GUID: orb1600968305933
Ixiasoft
7.14.2. Transceiver Reconfiguration Interfaces
Asserting the i_reconfig_reset signal resets all transceiver reconfiguration control and status registers, including the statistics counters; while this reset is in process, reads and writes to addresses in the F-Tile Ethernet Intel® FPGA Hard IP is delayed.
Port Name | Width | Description |
---|---|---|
i_reconfig_xcvrn_addr[17:0] |
18 bits | Address bus for transceiver control and status registers. |
i_reconfig_xcvrn_read |
1 bit | Transceiver read signal. When asserted, starts a read cycle. |
i_reconfig_xcvrn_write |
1 bit | Transceiver write signal. When asserted, writes data on the reconfiguration write data bus. |
i_reconfig_xcvrn_byteenable[3:0] |
4 bits | Transceiver byte enable signal for read and write request. |
o_reconfig_xcvrn_readdata[31:0] |
32 bits | Transceiver read data bus. When asserted, presents transceiver data read on a read cycle. |
o_reconfig_xcvrn_readdata_valid |
1 bit | Read data from Transceiver read data bus is valid. |
i_reconfig_xcvrn_writedata[31:0] |
32 bits | Transceiver write data bus. When asserted, presents transceiver data written on a write cycle. |
o_reconfig_xcvrn_waitrequest |
1 bit | Indicates the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low. |