F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History for F-Tile Ethernet Intel® FPGA Hard IP User Guide
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion 4.2.1.7. TX Packing Logic
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Deterministic Latency Interface 7.13. 32-bit Soft CWBIN Counters 7.14. Reconfiguration Interfaces 7.15. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.14. Reconfiguration Interfaces x
7.14.1. Ethernet Reconfiguration Interfaces 7.14.2. Transceiver Reconfiguration Interfaces
7.15. Precision Time Protocol Interface x
7.15.1. Time-of-Day Interface 7.15.2. TX 2-Step Timestamp Interface 7.15.3. TX 1-Step Timestamp Interface 7.15.4. RX Timestamp Interface 7.15.5. PTP Status Interface 7.15.6. PTP Tile Interface
7.15.3. TX 1-Step Timestamp Interface x
7.15.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History for F-Tile Ethernet Intel® FPGA Hard IP User Guide

7.10. FlexE and OTN Mode RX Interface

The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in FlexE and OTN variations employs the PCS66 interface protocol.

The FlexE and 200GE/400GE OTN modes, the application allows to read 66b blocks from the RX PCS, bypassing the RX MAC.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Additionally, the OTN mode enables the collection of RX MAC statistics.

Table 52.  Signals of the PCS66 RX InterfaceAll interface signals are clocked by the RX clock. The signal names are standard Avalon-ST signals.

Name

Width

Description

o_rx_pcs66_d[1055:0]

o_rx_pcs66_d[527:0]

o_rx_pcs66_d[263:0]

o_rx_pcs66_d[131:0]

o_rx_pcs66_d[65:0]

1056 bits (400GE)

528 bits (200GE)

264 bits (100GE)

132 bits (40GE/50GE)

66 bits(10GE/25GE)

RX PCS 66b data for 1 block.

  • In FlexE mode, the RX PCS 66b data is aligned and descrambled but not decoded.
  • In OTN mode, the RX PCS 66b data is aligned and descrambled in 200GE/400GE.

o_rx_pcs66_valid

1 bit When asserted, indicates that the RX PCS 66b data is valid.

o_rx_pcs66_am_valid

1 bit Alignment marker indicator.

When asserted, Indicates the blocks on the RX PCS 66b data signal are identified as RS-FEC codeword markers.

Figure 47. Receiving Data Using the PCS66 RX InterfaceThe figure shows how to read the 66b blocks directly from the RX PCS using the PCS mode RX Interface.

The 66b blocks follow Ethernet 64b/66b convention. The least significant 2 bits of each 66 block is a 2b sync header and the remaining 64b are data.

  • In FlexE mode, the data is aligned and descrambled..
  • In OTN mode, the data is aligned and descrambled in 200GE/400GE.

The data is only valid when o_rx_pcs66_valid is high. The contents of the o_rx_pcs66_d bus are not defined when o_rx_pcs66_valid is low.

The block order for the PCS66 mode RX interface is the same as the RX PCS interface. Blocks flow from LSB to MSB; the first block that the core receives is o_rx_pcs66_d[65:0].

The bit order for the PCS66 mode RX interface is the same as the RX PCS interface. Bits flow from least to most significant; the first bit that the core receives is o_rx_pcs66_d[0].

o_rx_pcs66_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_pcs66_valid. When o_rx_pcs66_valid is low, o_rx_pcs66_am_valid is not valid.

  • In FlexE mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d is undefined because the alignment markers do not get descrambled.
  • In OTN mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d presents the received alignment markers.
Figure 48. Receiving Alignment Markers for FlexE Mode
Figure 49. Receiving Alignment Markers for OTN Mode
Level Two Title