Use the provided design files to run the reference design. Intel also provides precompiled a10_dp_demo.sof and dp_demo.elf files as part of the project file in the master_image directory.

1. Configure your PC to produce an image at resolution of 1920 × 1080.
2. Install the Bitec FMC daughter card at FMC port A of the development kit.
3. Install the DDR4 HiLo module onto the development kit.
4. Connect the development kit to your PC using a micro USB cable.
5. Connect the DisplayPort cable from your monitor to the TX DisplayPort connector on the FMC daughter card.
6. Connect the DisplayPort cable from your PC to the RX DisplayPort connector on the FMC daughter card.
7. Power up the development kit.
8. Extract the reference design to your PC.
9. Launch the Nios II command shell. Navigate to the script directory in the reference design project folder.
10. Load the design into the FPGA by typing ./rerun.sh at the Nios II command shell.
    1. To use the precompiled a10_dp_demo.sof and dp_demo.elf files, make sure the files are in the following directory in the rerun.sh script:
       SOPC_DIR=../master_image
       APP_DIR=../master_image
    2. To use your own compiled .sof file and rebuild the .elf file, make sure the files are in the following directory in the rerun.sh script and the name of the .sof file is correct:
       SOPC_DIR=../quartus
       APP_DIR=../software/dp_demo
       SOF_NAME=top.sof
11. The script loads the .sof file, then the .elf file and launches the Nios II terminal.
    Note: If you have more than 1 development kit or Intel® FPGA Download Cable connected to your PC, you need to type ./rerun.sh<USB cable number> . To find the cable number, type jtagconfig at the DOS command prompt.
12. Extract the dp_demo.zip file and place the extracted folders in the software folder. The dp_demo.zip file contains the .hex file for the Nios II software image. (Optional)