Cyclone® V GX, GT, and E Device Errata

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ID 683015
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata x
1.1. TLP Corruption in x2 Mode 1.2. JTAG Programming of 28-nm Devices 1.3. Signal Detect Issue in PCIe Configuration 1.4. External Memory Interface (EMIF) Maximum Frequency Specification Update 1.5. Fractional PLL Phase Alignment Error 1.6. Configuration via Protocol (CvP) 1.7. Usermode High Icc 1.8. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.9. Revision History for Cyclone® V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata

1.3. Signal Detect Issue in PCIe Configuration

The Signal Detect (SD) circuit required in PCIe Configuration (Hard IP and PIPE mode) may switch OFF under the following conditions:

  • Low temperature
  • Upper limit of VCCER_GXB (receiver buffer power supply voltage)

PCIe link training may not be fully completed in the case where the SD circuit remains de-asserted or remains OFF with an incoming signal.

This issue is a time-zero condition. If shipped devices have been tested not to show this issue initially, it will not show in the future.

Workaround

Update the Intel® Quartus® Prime settings for receiver common mode voltage (RX Vcm) and receiver signal detect circuit threshold (RX Vth) settings as shown in the following table.

Device VCCER_GXB RX Vcm Voltage RX Vth Settings
Cyclone® V GT/ST 1.2 V 0.75 V 4

To update RX Vcm and RX Vth settings, refer to the KDB solution.

If you are unable to make changes to resolve the issue, contact Intel® Premier Support for additional information.

Status

Affects: Cyclone® V GT/ST devices

There is no planned fix for this issue.

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