1.5. Fractional PLL Phase Alignment Error
Description
The fPLL has a silicon sensitivity that causes the static phase error to operate beyond the Quartus® II software expectation. The frequency range and jitter performance of the fPLL meet the Cyclone® V Device Datasheet specifications. This sensitivity is a time zero failure, which means a design affected by this issue will show failure immediately upon a given device operation over expected operating conditions or will never show the issue.
The following usage modes may be affected:
- When the fPLL is used for phase compensation. For example, applications that may use phase compensation include LVDS, board trace matching, or FPGA skew compensation, such as zero delay buffering.
- Specific IP cores that require fPLL usage.
- Inter-clock domain transfers involving fPLL usage.
Workaround
You can implement design techniques to mitigate inter-clock domain transfers and use the Intel® tool to evaluate fPLL usage and determine if designs may be affected by this issue.
Note: To determine if your design may be affected, use the Altera fPLL Usage Evaluation Tool.
If you believe your design is affected by this issue, please contact Intel® Premier Support for further assistance.
Status
Affects: Cyclone® V GX, GT, and E devices
This issue is fixed in the silicon die revision shown below.
| Family | Device | Fixed Die Revision |
|---|---|---|
| Cyclone V GT | 5CGTD9 | B |
| 5CGTD7 | C | |
| 5CGTD5 | B | |
| Cyclone V GX | 5CGXC9 | B |
| 5CGXC7 | C | |
| 5CGXC5 | B | |
| 5CGXC4 | B | |
| 5CGXC3 | B | |
| Cyclone V E | 5CEA9 | B |
| 5CEA7 | C | |
| 5CEA5 | B | |
| 5CEA4 | B | |
| 5CEA2 | B |
Figure 1. Altera Date Code Marking FormatThis figure explains the date code and revision marking format.