AN 831: Intel® FPGA SDK for OpenCL™: Host Pipelined Multithread

Download PDF
ID 683013
Date 11/20/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread x
1.1. Introduction 1.2. Pipelining Framework for High Throughput Design 1.3. Optimization Techniques for CPU Tasks 1.4. Design Example: Data Compression Algorithm 1.5. Document Revision History
1.3. Optimization Techniques for CPU Tasks x
1.3.1. Processor Affinity or CPU Pinning 1.3.2. Cache Optimizations
1.4. Design Example: Data Compression Algorithm x
1.4.1. Host Channel Streaming Feature 1.4.2. Pipelining Framework Details 1.4.3. Fine Tuning the Framework Design 1.4.4. Performance Evaluation
1.4.3. Fine Tuning the Framework Design x
1.4.3.1. Huffman Code (Tree) Generation 1.4.3.2. Processor Affinity in GZIP
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread

1.4.3.2. Processor Affinity in GZIP

In a high-throughput design, Processor Affinity enables assigning each thread loop to a specific core.

As mentioned earlier, Huffman code generation, kernel execution, and metadata generation, all execute a thread loop that reads or consumes data object from an input queue and delivers the processed data or job item to an output queue that acts as an input queue for the next stage in the pipeline. Along with these thread loops, the frequency counter in Huffman code generation uses up to three threads internally to obtain high-throughput. These threads are also assigned to specific cores for optimal performance, as mentioned earlier.

Related Information
Level Two Title