AN 831: Intel® FPGA SDK for OpenCL™: Host Pipelined Multithread

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ID 683013
Date 11/20/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread x
1.1. Introduction 1.2. Pipelining Framework for High Throughput Design 1.3. Optimization Techniques for CPU Tasks 1.4. Design Example: Data Compression Algorithm 1.5. Document Revision History
1.3. Optimization Techniques for CPU Tasks x
1.3.1. Processor Affinity or CPU Pinning 1.3.2. Cache Optimizations
1.4. Design Example: Data Compression Algorithm x
1.4.1. Host Channel Streaming Feature 1.4.2. Pipelining Framework Details 1.4.3. Fine Tuning the Framework Design 1.4.4. Performance Evaluation
1.4.3. Fine Tuning the Framework Design x
1.4.3.1. Huffman Code (Tree) Generation 1.4.3.2. Processor Affinity in GZIP
1. Intel® FPGA SDK for OpenCL™ Host Pipelined Multithread

1.4.1. Host Channel Streaming Feature

Communication between a host and a device is usually a time consuming, especially for large sized data.

Input data is transferred from the host memory into the global memory on the device. To use the data, kernels access this global memory and copy the required data into their local memory. This process of transferring data adds a huge latency since the whole data must be transferred from the host to global memory before starting any process on the device. The same latency is observed for the output data since the whole output must be generated first, saved into the global memory and then, transferred into the host memory.

The following figure illustrates the host channel streaming feature and how it provides a lower overhead by eliminating the need to access global memory. When you implement this feature, kernel is launched only once into the device and used for multiple input files, as they are streamed directly into the device from the host.

Figure 6. Host Channel vs Memory-Based Data Communication

Intel® FPGA SDK for OpenCL™ supports streaming data between a host and a device to eliminate the global memory access in both directions and directly pass data to the local memory through host channels, and also read back from the device. This reduces latency and enables platform (CPU or FPGA) to start processing the streamed data.

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