Visible to Intel only — GUID: GUID-98264D04-5215-4C3C-8A45-C63F43ABD7B0
Abs
AbsBackward
Add
AvgPool
AvgPoolBackward
BatchNormForwardTraining
BatchNormInference
BatchNormTrainingBackward
BiasAdd
BiasAddBackward
Clamp
ClampBackward
Concat
Convolution
ConvolutionBackwardData
ConvolutionBackwardWeights
ConvTranspose
ConvTransposeBackwardData
ConvTransposeBackwardWeights
Dequantize
Divide
DynamicDequantize
DynamicQuantize
Elu
EluBackward
End
Exp
GELU
GELUBackward
HardSigmoid
HardSigmoidBackward
HardSwish
HardSwishBackward
Interpolate
InterpolateBackward
LayerNorm
LayerNormBackward
LeakyReLU
Log
LogSoftmax
LogSoftmaxBackward
MatMul
Maximum
MaxPool
MaxPoolBackward
Minimum
Mish
MishBackward
Multiply
Pow
PReLU
PReLUBackward
Quantize
Reciprocal
ReduceL1
ReduceL2
ReduceMax
ReduceMean
ReduceMin
ReduceProd
ReduceSum
ReLU
ReLUBackward
Reorder
Round
Select
Sigmoid
SigmoidBackward
SoftMax
SoftMaxBackward
SoftPlus
SoftPlusBackward
Sqrt
SqrtBackward
Square
SquaredDifference
StaticReshape
StaticTranspose
Subtract
Tanh
TanhBackward
TypeCast
Wildcard
enum dnnl_alg_kind_t
enum dnnl_normalization_flags_t
enum dnnl_primitive_kind_t
enum dnnl_prop_kind_t
enum dnnl_query_t
enum dnnl::normalization_flags
enum dnnl::query
struct dnnl_exec_arg_t
struct dnnl_primitive
struct dnnl_primitive_desc
struct dnnl::primitive
struct dnnl::primitive_desc
struct dnnl::primitive_desc_base
enum dnnl_rnn_direction_t
enum dnnl_rnn_flags_t
enum dnnl::rnn_direction
enum dnnl::rnn_flags
struct dnnl::augru_backward
struct dnnl::augru_forward
struct dnnl::gru_backward
struct dnnl::gru_forward
struct dnnl::lbr_augru_backward
struct dnnl::lbr_augru_forward
struct dnnl::lbr_gru_backward
struct dnnl::lbr_gru_forward
struct dnnl::lstm_backward
struct dnnl::lstm_forward
struct dnnl::rnn_primitive_desc_base
struct dnnl::vanilla_rnn_backward
struct dnnl::vanilla_rnn_forward
Visible to Intel only — GUID: GUID-98264D04-5215-4C3C-8A45-C63F43ABD7B0
convolution cpp
Annotated version: Convolution Primitive Example
Annotated version: Convolution Primitive Example
/*******************************************************************************
* Copyright 2020-2022 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <algorithm>
#include <cmath>
#include <iostream>
#include <string>
#include <vector>
#include "example_utils.hpp"
#include "oneapi/dnnl/dnnl.hpp"
using namespace dnnl;
using tag = memory::format_tag;
using dt = memory::data_type;
void convolution_example(dnnl::engine::kind engine_kind) {
// Create execution dnnl::engine.
dnnl::engine engine(engine_kind, 0);
// Create dnnl::stream.
dnnl::stream engine_stream(engine);
// Tensor dimensions.
const memory::dim N = 3, // batch size
IC = 32, // input channels
IH = 13, // input height
IW = 13, // input width
OC = 64, // output channels
KH = 3, // weights height
KW = 3, // weights width
PH_L = 1, // height padding: left
PH_R = 1, // height padding: right
PW_L = 1, // width padding: left
PW_R = 1, // width padding: right
SH = 4, // height-wise stride
SW = 4, // width-wise stride
OH = (IH - KH + PH_L + PH_R) / SH + 1, // output height
OW = (IW - KW + PW_L + PW_R) / SW + 1; // output width
// Source (src), weights, bias, and destination (dst) tensors
// dimensions.
memory::dims src_dims = {N, IC, IH, IW};
memory::dims weights_dims = {OC, IC, KH, KW};
memory::dims bias_dims = {OC};
memory::dims dst_dims = {N, OC, OH, OW};
// Strides, padding dimensions.
memory::dims strides_dims = {SH, SW};
memory::dims padding_dims_l = {PH_L, PW_L};
memory::dims padding_dims_r = {PH_R, PW_R};
// Allocate buffers.
std::vector<float> src_data(product(src_dims));
std::vector<float> weights_data(product(weights_dims));
std::vector<float> bias_data(OC);
std::vector<float> dst_data(product(dst_dims));
// Initialize src, weights, and dst tensors.
std::generate(src_data.begin(), src_data.end(), []() {
static int i = 0;
return std::cos(i++ / 10.f);
});
std::generate(weights_data.begin(), weights_data.end(), []() {
static int i = 0;
return std::sin(i++ * 2.f);
});
std::generate(bias_data.begin(), bias_data.end(), []() {
static int i = 0;
return std::tanh(float(i++));
});
// Create memory objects for tensor data (src, weights, dst). In this
// example, NCHW layout is assumed for src and dst, and OIHW for weights.
auto user_src_mem = memory({src_dims, dt::f32, tag::nchw}, engine);
auto user_weights_mem = memory({weights_dims, dt::f32, tag::oihw}, engine);
auto user_dst_mem = memory({dst_dims, dt::f32, tag::nchw}, engine);
// Create memory descriptors with format_tag::any for the primitive. This
// enables the convolution primitive to choose memory layouts for an
// optimized primitive implementation, and these layouts may differ from the
// ones provided by the user.
auto conv_src_md = memory::desc(src_dims, dt::f32, tag::any);
auto conv_weights_md = memory::desc(weights_dims, dt::f32, tag::any);
auto conv_dst_md = memory::desc(dst_dims, dt::f32, tag::any);
// Create memory descriptor and memory object for input bias.
auto user_bias_md = memory::desc(bias_dims, dt::f32, tag::a);
auto user_bias_mem = memory(user_bias_md, engine);
// Write data to memory object's handle.
write_to_dnnl_memory(src_data.data(), user_src_mem);
write_to_dnnl_memory(weights_data.data(), user_weights_mem);
write_to_dnnl_memory(bias_data.data(), user_bias_mem);
// Create primitive post-ops (ReLU).
const float alpha = 0.f;
const float beta = 0.f;
post_ops conv_ops;
conv_ops.append_eltwise(algorithm::eltwise_relu, alpha, beta);
primitive_attr conv_attr;
conv_attr.set_post_ops(conv_ops);
// Create primitive descriptor.
auto conv_pd = convolution_forward::primitive_desc(engine,
prop_kind::forward_training, algorithm::convolution_direct,
conv_src_md, conv_weights_md, user_bias_md, conv_dst_md,
strides_dims, padding_dims_l, padding_dims_r, conv_attr);
// For now, assume that the src, weights, and dst memory layouts generated
// by the primitive and the ones provided by the user are identical.
auto conv_src_mem = user_src_mem;
auto conv_weights_mem = user_weights_mem;
auto conv_dst_mem = user_dst_mem;
// Reorder the data in case the src and weights memory layouts generated by
// the primitive and the ones provided by the user are different. In this
// case, we create additional memory objects with internal buffers that will
// contain the reordered data. The data in dst will be reordered after the
// convolution computation has finalized.
if (conv_pd.src_desc() != user_src_mem.get_desc()) {
conv_src_mem = memory(conv_pd.src_desc(), engine);
reorder(user_src_mem, conv_src_mem)
.execute(engine_stream, user_src_mem, conv_src_mem);
}
if (conv_pd.weights_desc() != user_weights_mem.get_desc()) {
conv_weights_mem = memory(conv_pd.weights_desc(), engine);
reorder(user_weights_mem, conv_weights_mem)
.execute(engine_stream, user_weights_mem, conv_weights_mem);
}
if (conv_pd.dst_desc() != user_dst_mem.get_desc()) {
conv_dst_mem = memory(conv_pd.dst_desc(), engine);
}
// Create the primitive.
auto conv_prim = convolution_forward(conv_pd);
// Primitive arguments.
std::unordered_map<int, memory> conv_args;
conv_args.insert({DNNL_ARG_SRC, conv_src_mem});
conv_args.insert({DNNL_ARG_WEIGHTS, conv_weights_mem});
conv_args.insert({DNNL_ARG_BIAS, user_bias_mem});
conv_args.insert({DNNL_ARG_DST, conv_dst_mem});
// Primitive execution: convolution with ReLU.
conv_prim.execute(engine_stream, conv_args);
// Reorder the data in case the dst memory descriptor generated by the
// primitive and the one provided by the user are different.
if (conv_pd.dst_desc() != user_dst_mem.get_desc()) {
reorder(conv_dst_mem, user_dst_mem)
.execute(engine_stream, conv_dst_mem, user_dst_mem);
} else
user_dst_mem = conv_dst_mem;
// Wait for the computation to finalize.
engine_stream.wait();
// Read data from memory object's handle.
read_from_dnnl_memory(dst_data.data(), user_dst_mem);
}
void depthwise_convolution_example(dnnl::engine::kind engine_kind) {
// Create execution dnnl::engine.
dnnl::engine engine(engine_kind, 0);
// Create dnnl::stream.
dnnl::stream engine_stream(engine);
// Tensor dimensions.
const memory::dim N = 3, // batch size
G = 32, // channel groups
IC = 32, // input channels
IH = 13, // input height
IW = 13, // input width
OC = 32, // output channels
KH = 3, // weights height
KW = 3, // weights width
PH_L = 1, // height padding: left
PH_R = 1, // height padding: right
PW_L = 1, // width padding: left
PW_R = 1, // width padding: right
SH = 4, // height-wise stride
SW = 4, // width-wise stride
OH = (IH - KH + PH_L + PH_R) / SH + 1, // output height
OW = (IW - KW + PW_L + PW_R) / SW + 1; // output width
// Source (src), weights, bias, and destination (dst) tensors dimensions.
memory::dims src_dims = {N, IC, IH, IW};
memory::dims weights_dims = {G, OC / G, IC / G, KH, KW};
memory::dims bias_dims = {OC};
memory::dims dst_dims = {N, OC, OH, OW};
// Strides, padding dimensions.
memory::dims strides_dims = {SH, SW};
memory::dims padding_dims_l = {PH_L, PW_L};
memory::dims padding_dims_r = {PH_R, PW_R};
// Allocate buffers.
std::vector<float> src_data(product(src_dims));
std::vector<float> weights_data(product(weights_dims));
std::vector<float> bias_data(OC);
std::vector<float> dst_data(product(dst_dims));
// Initialize src, weights, and dst tensors.
std::generate(src_data.begin(), src_data.end(), []() {
static int i = 0;
return std::cos(i++ / 10.f);
});
std::generate(weights_data.begin(), weights_data.end(), []() {
static int i = 0;
return std::sin(i++ * 2.f);
});
std::generate(bias_data.begin(), bias_data.end(), []() {
static int i = 0;
return std::tanh(float(i++));
});
// Create memory objects for tensor data (src, weights, dst). In this
// example, NCHW layout is assumed for src and dst, and OIHW for weights.
auto user_src_mem = memory({src_dims, dt::f32, tag::nchw}, engine);
auto user_weights_mem = memory({weights_dims, dt::f32, tag::goihw}, engine);
auto user_dst_mem = memory({dst_dims, dt::f32, tag::nchw}, engine);
// Create memory descriptors with format_tag::any for the primitive. This
// enables the convolution primitive to choose memory layouts for an
// optimized primitive implementation, and these layouts may differ from the
// ones provided by the user.
auto conv_src_md = memory::desc(src_dims, dt::f32, tag::any);
auto conv_weights_md = memory::desc(weights_dims, dt::f32, tag::any);
auto conv_dst_md = memory::desc(dst_dims, dt::f32, tag::any);
// Create memory descriptor and memory object for input bias.
auto user_bias_md = memory::desc(bias_dims, dt::f32, tag::a);
auto user_bias_mem = memory(user_bias_md, engine);
// Write data to memory object's handle.
write_to_dnnl_memory(src_data.data(), user_src_mem);
write_to_dnnl_memory(weights_data.data(), user_weights_mem);
write_to_dnnl_memory(bias_data.data(), user_bias_mem);
// Create primitive post-ops (ReLU).
const float alpha = 0.f;
const float beta = 0.f;
post_ops conv_ops;
conv_ops.append_eltwise(algorithm::eltwise_relu, alpha, beta);
primitive_attr conv_attr;
conv_attr.set_post_ops(conv_ops);
// Create primitive descriptor.
auto conv_pd = convolution_forward::primitive_desc(engine,
prop_kind::forward_training, algorithm::convolution_direct,
conv_src_md, conv_weights_md, user_bias_md, conv_dst_md,
strides_dims, padding_dims_l, padding_dims_r, conv_attr);
// For now, assume that the src, weights, and dst memory layouts generated
// by the primitive and the ones provided by the user are identical.
auto conv_src_mem = user_src_mem;
auto conv_weights_mem = user_weights_mem;
auto conv_dst_mem = user_dst_mem;
// Reorder the data in case the src and weights memory layouts generated by
// the primitive and the ones provided by the user are different. In this
// case, we create additional memory objects with internal buffers that will
// contain the reordered data. The data in dst will be reordered after the
// convolution computation has finalized.
if (conv_pd.src_desc() != user_src_mem.get_desc()) {
conv_src_mem = memory(conv_pd.src_desc(), engine);
reorder(user_src_mem, conv_src_mem)
.execute(engine_stream, user_src_mem, conv_src_mem);
}
if (conv_pd.weights_desc() != user_weights_mem.get_desc()) {
conv_weights_mem = memory(conv_pd.weights_desc(), engine);
reorder(user_weights_mem, conv_weights_mem)
.execute(engine_stream, user_weights_mem, conv_weights_mem);
}
if (conv_pd.dst_desc() != user_dst_mem.get_desc()) {
conv_dst_mem = memory(conv_pd.dst_desc(), engine);
}
// Create the primitive.
auto conv_prim = convolution_forward(conv_pd);
// Primitive arguments.
std::unordered_map<int, memory> conv_args;
conv_args.insert({DNNL_ARG_SRC, conv_src_mem});
conv_args.insert({DNNL_ARG_WEIGHTS, conv_weights_mem});
conv_args.insert({DNNL_ARG_BIAS, user_bias_mem});
conv_args.insert({DNNL_ARG_DST, conv_dst_mem});
// Primitive execution: convolution with ReLU.
conv_prim.execute(engine_stream, conv_args);
// Reorder the data in case the dst memory descriptor generated by the
// primitive and the one provided by the user are different.
if (conv_pd.dst_desc() != user_dst_mem.get_desc()) {
reorder(conv_dst_mem, user_dst_mem)
.execute(engine_stream, conv_dst_mem, user_dst_mem);
} else
user_dst_mem = conv_dst_mem;
// Wait for the computation to finalize.
engine_stream.wait();
// Read data from memory object's handle.
read_from_dnnl_memory(dst_data.data(), user_dst_mem);
}
int main(int argc, char **argv) {
auto exit_code = handle_example_errors(
convolution_example, parse_engine_kind(argc, argv));
if (exit_code != 0) return exit_code;
return handle_example_errors(
depthwise_convolution_example, parse_engine_kind(argc, argv));
}